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LM5115: Sub-harmonic oscillation at high VIN and with higher output currents

Christopher Richardson
Intellectual 360 points
Part Number: LM5115

Dear E2E,

     I'm testing an LM5115 operating as an SSPR where the main converter is an active clamp forward. The VIN to the forward is 38V to 140V, and the forward xfmr has a 2:1 ratio. The output voltage of the forward converter is 12V. The output voltage of the SSPR is 5.2V, and the maximum output current is 8.0A. I have taken great care to make sure that none of the abs max limits of the LM5115's pins are violated.

    At no-load, the SSPR works properly over the complete VIN range. Once I increase the load to about 2.5A, though, the SSPR's duty cycle shows a sub-harmonic oscillation that begins as VIN increases past around 125V, and then doesn't stop until VIN has been decreased back down below about 100V. At the maximum load of 8A, the sub-harmonic oscillation begins as VIN increases past around 100V and doesn't go back to regular pulse widths until VIN has dropped below around 80V. In the following plots, SW1 is the "phase" signal as it's referred to in the LM5115 datasheet, and SW3 is the switch node of the SSPR itself.

So far, I've confirmed to my satisfaction that the outer voltage control loop is not at fault, as about one year ago David Baba sent me a MathCAD model, and with this I was able to set the control loop compensation, and the load step response looks fine:

I have also tried added filtering on the current sense inputs, as well as reducing the current sense resistance to 1/2 of its normal value, and none of these things change the sub-harmonic oscillation. Therefore, I have discounted the current limit as a possible culprit. I'm not sure how to test to see if the negative current limit could be at fault.

     Is it possible that 600 ns is around the minimum stable on-time?

I'm not allowed to post the actual schematic in a public forum, however using this one from the datasheet:

My values are: fsw = 136 kHz, VBIAS from regulated 10V source, C4 = 470 pF, current sense = 3 mohm, R4 = 499k, added 220 pF from CO to GND, C7 = 22 nF, R3 = 33k, L1 = 8.2 uH, total Cout = 940 uF and total ESR around 8 mohm

Any other possible causes of this sub-harmonic oscillation?

Thanks,

Chris

  • 0
    TI__Mastermind 27115 points

    Hi Chris,

    Can you upload the image again? 

    B R

    Andy

  • 0 in reply to Andy Chen
    Intellectual 360 points

    PID sub-harmonic oscillation 2020-04-21.pdf

    Hi Andy,

        All the images were in a PDF, so I've attached that, and I hope it comes through properly. While I'm writing, let me clarify that the schematic I'm using for your reference is Figure 21 on p.16 of the LM5115 datasheet. I forgot to note the output resistor divider values and they're critical for the control loop compensation. Those are:

    R12 = 18kohm, R13 = 3kohm

    Thanks,

    chris

  • 0 in reply to Christopher Richardson
    TI__Mastermind 27115 points

    Hi Chris,

    Unstable switching should be caused by noise or unstable control loop.

    I roughly check your external components and have below suggestions:

    1. C4 390pF

    2. C7 47nF ? do you have estimation of your primary converter loop cross over freq?

    3. What's saturation current of L1? it shoul be >15A if Rsense=3mohm.

    4. what's output capacitor combination? ceramic cap voltage rating>=16V

    5. can you upload PCB layout? screen short image is OK.

    B R

    Andy

  • 0 in reply to Andy Chen
    Intellectual 360 points

    Hi Andy,

    1. We will try with 390 pF for the RAMP cap, C4 in the LM5115 datasheet schematic

    2. I checked again with my customer to make sure, and our C7 value is 22 nF. I used a MathCAD model I got from David Baba to design the control loop. According to MathCAD, the bandwidth is around 6.5 kHz and the phase margin 90º - so very conservative - but I wanted it that way due to the very wide VIN range.

    3. L1 is a Bourns SRP1770TA-8R2M with 25A of saturation current

    4. The output caps are two 470 uF, 16 mohm polymer aluminum devices, PN PCF1A471MCL1GS in parallel. Also in parallel are two 1206, 10uF, 35V, X7R MLCC's whose total capacitance at 5.2V I'm estimating as around 10 uF. In my experience, adding this to the capacitance of the polymer caps works well for control loop design, and I leave the total output ESR as 16m/2 = 8 mohm

    5. The power path components are on the top layer, the LM5115 is on the bottom. There are two internal planes for heatsinking, all 2 oz copper.

    L6 is the power inductor, Q7,8,9 are the power FETs. I left the top solder paste mask on for the bottom side to show the careful differential routing of the current sense lines.

    Thanks,

    chris

  • 0 in reply to Christopher Richardson
    TI__Mastermind 27115 points

    Hi Chris,

    Do you know the bandwidth of main converter 12V output? NOT the SSPR bandwidth. C7 and R3 is determined by loop bandwidth of 12V output.

    B R

    Andy

  • 0 in reply to Andy Chen
    Intellectual 360 points

    Hi Andy,

        I estimate the forward converter's bandwidth to be between 4 kHz and 5 kHz, with a phase margin of around 60º. I can't get to my lab and test, unfortunately, because of COVID.

    Thanks,

    chris

  • 0 in reply to Christopher Richardson
    TI__Mastermind 27115 points

    Hi Chris,

    C7 and R3  should meet below:

    2*PI*R3*C7>(10/4KHz)

    R3=3Kohm, so C7>133nF.

    B R

    Andy