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# TL1963A: Thermal design help

Part Number: TL1963A

Customer wants to convert Vin = 10.8V to 13.2V to Vout = 9V using multiple TL1963A. Output load = 1.2A.  Tambient = 45degC.

One approach is to cascade two TL1963A LDOs (in KTT package) in series to share the power dissipation.  Both LDOs would share a thermal pad on the topside of the board just large enough to encase the two packages.  The pad would have about 20 thermal vias down to layer 7 of an 8 layer board. Layer 7 is almost all ground plane (>2500 sqmm).

An alternate approach would be to use three TL1963A devices in parallel to share the load. All three would handle the full In/Output drop, but would output to different circuits so no load ballast is required. Each LDO would handle about 400 mA load current. Topside thermal pad would be just large enough to hold all three LDOs.

Which approach would we recommend? Customer would like to get away with just two LDOs for area reasons. Seems like using three LDOs would reduce junction temp of the LDOs, but may be largest solution considering size of device and needed input/output caps.

Its not clear how to model the thermal plan of the PCB. Will the thermal vias be enough to keep the topside thermal pad at a reasonable temp?

• Hey Mark,

It's great to hear they are already planning for multiple thermal vias, this is often missed by customers and has a significant effect. If the max ambient temperature is 45C, then they can probably get away with two LDO's in series. I'd recommend setting the first Vout to 10.2 so the min Vin-Vout=600mV which would keep it out of dropout and will reduce the power dissipation of the first stage when Vin increases to 13.2V. So using worst case we'd have 2.4W of dissipation (1.2A*[13.2V-10.2V]) and the Rja is 32.9C/W for the JEDEC high-k board. So using Tj=Ta+Pd*Rja this would result in a max junction temperature of 124C keeping it just below the max operating temp.

However, the description of their board sounds like it'll probably be better than the JEDEC high-k board and we have data showing that with a good thermal layout the Rja can be reduced by ~30% (see this app note if you're interested). While it would be better if the thermal vias were electrically connected to more metal, if the internal layers have a large amount of metal in and around the vias that metal will still help offload heat. Assuming the 30% improvement would result in a max junction temp of 99C.

So their max junction temp should be between 99C-124C, keeping them within the specification. The last thing to consider is how often the LDOs are going to be running at these extended temperatures (this would be a combination of how often the 1.2A at Vin=13.2V is being applied and how often the ambient temp is at the max of 45C). Catalog IC's are qualified using the JEDEC standards JESD22-A108 and JESD85 which ensures IC's can operate at Tj=55C for approximately 9 years but the lifetime decreases as the temperature increases (which is often overlooked). Just to give you a sense of the effect junction temp has on IC lifetime below is a graph showing the minimum lifetime vs junction temp based on the JEDEC standards.

Let me know if you have any other questions.

• Hi Kyle,

Thanks for the thorough analysis and comments.   This is really helpful.  However,  there may be an error in the calculations.

Under the worst case of Vin = 13.2V, the power dissipation in the first LDO would be 1.2A(13.2-10.2) = 3.6W instead of 2.4W.  Under the RjA assumption of 32.9 degC/W, this results in a much higher junction temp (163C). Even with a 30% improvement in Rja, the junction temp might exceed 125C.

Did I overlook something when I was going through this?

• Hey Mark,

Sorry about that, some how I made a silly error and miscalculated the power dissipation, you are right it should be 3.6W which takes it ~1 degree beyond the rated junction temperature  (126C) even with the best PCB layout case. So if they really optimize the board for thermals they'll be right at or above the max junction temperature which wouldn't really result in much of a difference from a performance point of view however it makes the comments I made previously on minimum lifetime even more relevant.

So they'll need to do the analysis themselves to determine how they'd like to proceed however I'd suggest going with the three parallel LDOs. This topology would burn 1.2W of power dissipation per LDO and if we assume the PCB is only as good as the JEDEC board then we'd expect a max junction temp of ~83C so there is a significant amount of margin with this design.