• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Subscribers 63 subscribers
  • Views 642 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPS53819A: How does OCP TPS53819A work

Yang Wu
Intellectual 2840 points
Part Number: TPS53819A

Hi team,

I have a question about the OCP functionality.

The DS says " TPS53819A has cycle-by-cycle overcurrent limiting control. The inductor current is monitored during the OFF state."

My question is that how the device decides that OCP should be triggered? Or say what's the exact time that the inductor current is monitored?

One idea is that,  the device will monitor the inductor current during the whole OFF period, the OCP will be triggered only if inductor current of the whole OFF period is larger than OCP trip level.

Another idea is the device will monitor the inductor current during the whole OFF period, but the OCP will be triggered only needs the vally point of inductor current is larger than OCP trip level.

thanks a lot.

Yang

  • 0
    TI__Mastermind 48200 points

     

    The TPS53819A uses a cycle by cycle, Off-time, valley current limit mechanism that limits the inductor current and places the converter into a constant output current mode until the load current decreases or the output voltage drops sufficiently to trigger the output under voltage protection fault.

    After an On-time completes, the highside FET turns off and the low-side FET turns on, there are 3 signals gating the start of a new On-time.  When all 3 conditions are met, a new on-time starts.

    1) Minimum Off-time of 320ns (typ).  This ensures enough time for the On-time energy to be reflected on the output voltage and for the current sense on the low-side FET to stabilize.

    2) Current Limit programmed by the TRIP pin. The voltage on the SW pin during the low-side FET on-time is compared to a scaled version of the voltage on the TRIP pin to set the current limit.  If the negative voltage on switch pin exceeds the current limit threshold, the Off-time will be extended until the inductor current drops below the current limit, limiting the inductor valley current during the off-time.

    3) The Reference Voltage.  This generates a new on-time when the output voltage is below the target output voltage as long as the minimum off-time has been met and the inductor current is less than the current limit.

    OCP is "triggered" when Conditions 1 and 3 are met, but Condition 2 is not because the inductor current is still above the Over Current Limit threshold when the reference attempts to trigger a new on-time.

    So, the current is actually sensed continuously during the low-side FET on-time, but it only affects operation when the inductor current exceeds the current-limit when a new on-time would be created.  By extending the off-time to limit the inductor current, the duty cycle is increased, reducing the output voltage until it triggers under-voltage protection.  This ensures a smooth transition from D-CAP regulation to pulse by pulse valley current limit while limiting the inductor current to protect against saturation and allowing the output capacitors to help ride through a momentary over-current condition, such as exceeding the current limit during a load-step recovery response.

  • 0 in reply to Peter James Miller
    TI__Intellectual 2840 points

    Hi Peter,

    Thanks for your detailed reply, it's very clear.

    One more thing, in the (2) condition, it says "The voltage on the SW pin during the on-time is compared to a scaled version of the voltage on the TRIP pin to set the current limit". Do you mean the low-side FET on time? In my opinion, it looks like low-side on-time since it says "If the negative voltage on switch....".

    Thanks a lot.

    Best regards,

    Yang

  • 0 in reply to Yang Wu
    TI__Intellectual 2840 points

    Clarification:

    In the (2) condition, it says "The voltage on the SW pin during the on-time is compared to a scaled version of the voltage on the TRIP pin to set the current limit".

    "on-time" mean the low-side FET on time.

  • 0 in reply to Yang Wu
    TI__Mastermind 48200 points

     

    I thought I answered, this but it seems I didn't, or it got lost.

    Yes, that should be low-side FET "On-time"  I will make sure to update my reply to correct it.