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# TPS546A24A: pin strapping

Part Number: TPS546A24A

I am trying to understand how to properly do pin strapping for TPS546A24A.  One confusion is what is regarding initial contents of EEPROM.  I think the default values for the EEPROM are in table 6.  Is this correct?  I am trying to figure out how to get the correct VSEL pin strapping.  The requirements I have is that the voltage is adjustable between 0.8 and 0.94V with 10mV step size.  Based on table 12 and the excel pinstrap calculator this does not seem possible but then table 13 seems like it should be possible.  Can you explain what the two tables are trying to convey? Thanks

• Hi Daniel,

Correct, table 6 shows the default values of the EEPROM for a new part.

I think the confusion is because the MINIMUM Vout and MAXIMUM Vout in table 12 and the VOUT_MIN and VOUT_MAX in table 13 have different meanings.

The values in table 12 are the minimum and maximum values that can be programmed for each ranges. So for example in table 12, the divider code 1 can be used to program between 0.75V to 0.9V in 15 steps of 10 mV. So resistor to ground code 0 adds 0mV to the 0.75V offset, R2G code 1 adds 10 mV, and so on. The resistor divider code 2 would be needed to program between 0.9 V and 0.94 V in 10 mV steps.

The values in table 13 are the VOUT_MIN and VOUT_MAX PMBus command values that are set when those resistor divider codes are selected.

I think I need some more details on what you are trying to do. Are you trying to change the output voltage in 10 mV steps while the device on and regulating the output voltage? Changing the VSEL resistors would only change the initial boot up output voltage. When the device is regulating, the PMBus command VOUT_COMMAND can be used to change the output voltage in 10 mV steps.

• Hi Anthony,

For this application I need to set it to 0.9V on initial startup and then during runtime the fpga will adjust the voltage between 0.75 and 0.94 in 10mV steps.  I am still somewhat confused from your description.  If I use resistor divider code 1 would I be able to set the voltage to 0.9V and have VOUT_MIN at 0.5V and VOUT_MAX at 1.5V?  What would VOUT_MODE be set at? Is that how the 10mV steps are set?

Thanks,

Dan

• So, the FPGA will change the output voltage through the PMBus interface? If that's right, you would just need to have VSEL resistors set the output voltage boot up value to 0.9V. After boot up, the output voltage can be changed through VOUT_COMMAND.

The max and min values in table 12 are the max and min values the pinstrap resistors can set to the VOUT_COMMAND initial boot voltage for that resistor divider code.

VOUT_MIN and VOUT_MAX are PMBus commands. These set the min and max values that can be programmed to VOUT_COMMAND through any method. More details on these commands are on page 66 and page 71 of the datasheet.

The default setting for VOUT_MODE is 0x97 which translates to relative format with an exponent of -9.