Hello TI Community
I am designing Battery Management System 100V/100A and planning to use MOSFET CSD19532KTT. I will mount the Mosfets on the PCB and Mosfets will be placed in Low Side. Please suggest the no of MOSFETS required in parallel. Also suggest suitable Low side driver for switching the MOSFETS.
Thanks in Advance
Hi Sandeep,
Thanks for the interest in TI FETs. First, if you're designing for 100V, then you may want to consider a higher voltage FET since you will have no margin for transients or other voltage variations using a 100V FET. General recommendation is to derate by 10% - 25% from the abs max VDS rating for the device to insure safe operation under all conditions. As a rule of thumb, at D2PAK can dissipate about 4W maximum as shown in the blog in the link below. With that in mind, we can calculate the number of parallel FETs required to conduct 100A as follows:
PD = (IDS) x (IDS) x Ron -> IDS = sqrt(PD/Ron) = sqrt(4W/(5.6mOhm x 2.1) = 18.4A, where 5.6mOhm is Ron max at VGS = 10V and 2.1 is the positive temperature coefficient of on resistance (see Figure 8 in the datasheet).
Assuming ideal current sharing, then the number of parallel FETs can be calculated as follows:
Number of FETs = 100A/18.4A = 5.42 which rounds up to 6 FETs in parallel.
TI has many low side driver ICs including LM5114 and UCC27518 (many other options in this family).
Hi Sandeep,
Below is a link to a blog on how we specify max continuous current and power dissipation on our FET datasheets. These are calculated quantities based on thermal impedance, max junction temperature, ambient (or case) temperature and rds(on). I used a similar approach and assumed RthetaJA around 20C/W, TJmax = 175C and Tamb = 100C. PD = (TJmax - Tamb)/RthetaJA = (175-100)/20 = 3.75W which is rounded up to 4W. I did some additional comparisons and this seems like a reasonable estimate for a good PCB layout using a D2PAK package.
TI's maximum BVDSS rating for TI FETs is 100V. We do not have any FETs with a higher voltage rating than 100V.
