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UCC21520-Q1: layout-isolation requirements

Dongbao Zhou
Expert 3930 points
Part Number: UCC21520-Q1

Hi team,

In some of my customer's design (old project), UCC21520-q1 didn't follow the recommendation, can you help explain what are the risks?

"To ensure isolation performance between the primary and secondary side, one should avoid placing any PCB traces or copper below the driver device. A PCB cutout is recommended in order to prevent contamination that may compromise the UCC21520-Q1’s isolation performance."

Besides, for the PCB cutout recommendation, does it related to capacitive isolation tech? How about transformer based and optocouple based?

Thanks

Dongbao

  • 0
    TI__Genius 10652 points

    Dongbao,

    Thanks for your question.

    The reason that copper pours or traces should not be routed underneath the IC package of isolated driver are that interference (such as from output switching transient) can be coupled onto low-voltage power ground planes and signal traces.

    Also: the driver package are also creepage and clearance, from package and leads for example, are critically related to the isolation ratings of the device. If traces or planes between HV and LV are routed under the IC it effectively reduces the function of the driver isolation.

    This concept is evident from narrowbody vs. widebody package. Even if the capacitive isolation inside the driver is rated at 5.7kVrms, if the leads of LV and HV side get closer and closer together, the conductors (leads) get closer and closer together, reducing the airgap, so the isolation of the driver can become a function of the package rather than the effectiveness of the isolation technology in the IC.

    This same concept goes for PCB traces, they are also conductors, seperated by a soldermask filled gap. The closer they get, the more the HV and LV side becomes coupled, and the less air/soldermask there to keep the HV side from arcing over and to minimize coupling.

    Routing power and signal under the driver could even result in arc/short from HV to LV side through the solder mask in situations where the driver would isolate this from the LV side or fail-open. it is always important to pay close attention to the PCB layout, because the gate driver is only part of the system.

    These concepts are equally applicable to transformer and optocoupler-based drivers as well. They are not exclusive to capacitive isolation.

    I hope this answers your question, let me know if you have any followup questions.

    Best

    Dimitri