TPS40057: About the Absolute Maximum Ratings for negative voltage at SWpin.

Kengo.Y

Guru 10735 points

Part Number: TPS40057
Other Parts Discussed in Thread: TPS40075,

Hi team.

I'd like to know about the Absolute Maximum Ratings for negative voltage at SWpin.

My customer has the negative voltage at SWpin of -1.6V for 120nsec.

Is this a problem?

Could you see the following waveform?

Voltage : 500mV/div

Time : 50ns/div

I'd like to confirm if we can make time to longer ,when the negative voltage is relax from the data sheet.

Sincerely.

Kengo.

over 4 years ago

0 Ankit Gupta95 over 4 years ago

TI__Expert 4555 points

Hello Kengo,

Absmax on the SW is about -2.5V. The waveform you have shown looks good to me.

Best Regards,

Ankit Gupta

0 Timothy Hegarty over 4 years ago

TI__Guru 60867 points

Hi Kengo,

Please ensure the measurement is made correctly using a low-noise scope probe setup (remove ground lead and use probe barrel for a close connection to GND). In general, such negative transients are sustained across the bond wire inductances. To mitigate the energy involved, use a tight layout with the input ceramic caps close to the FETs. See app note snva803 for power stage layout best practices.

Regards,

Tim

www.ti.com/lit/snva803

0 Kengo.Y over 4 years ago in reply to Ankit Gupta95

Guru 10735 points

Hi Ankit.

Thank you for your reply.

Absmax on the SW is about -2.5V.

-> According to data sheet, this rule has a time constraint(<50ns).

　Is that still a problem?

Sincerely.
Kengo.

0 Kengo.Y over 4 years ago in reply to Kengo.Y

Guru 10735 points

Hi Tim.

Thank you for your advice.

I'll give your advice to my customer.

Sincerely.

Kengo.

0 Kengo.Y over 4 years ago in reply to Kengo.Y

Guru 10735 points

Hi Ankit.

How about this question?

I want to get your answer ASAP.

By the way, other devices(TPS40075) have the following description.

Can we use this calculation method be applied to TPS40057?

Sincrely.

Kengo.

0 Timothy Hegarty over 4 years ago in reply to Kengo.Y

TI__Guru 60867 points

Hi Kengo,

I'm not sure where that spec came from. A transient of -1.6V for 120ns doesn't seem too stressful in my opinion. However, the recommendation is to reduce parasitic switching loop inductance to mitigate this transient behavior. See app note svva803 for guidance. In general, keep the input caps very close to the FETs and use a GND plane immediately below the power stage components.

Regards,

Tim

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TPS40057: About the Absolute Maximum Ratings for negative voltage at SWpin.