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LM73606-Q1: Time-out for loss of external SYNC

Part Number: LM73606-Q1
Other Parts Discussed in Thread: LM73605-Q1

The datasheet for this part indicates that if an external SYNC signal is being used but is frozen at logic high or logic low meaning no transitions occur, that after a "time-out" the part will revert back to its internal oscillator for SYNC. This is great and a very desirable behavior but I would like to know approximately how long this time-out period is so that I can assess whether I need to provide additional filtering or other protection to handle a brief loss of regulation that might occur during the switch-over. Also, when an external sync is provided I'm assuming that that hand-over happens instantaneously without a corresponding time-out to switch between internal and external sync?

  • Hello Brian,

    Recommendations for the external clock include a high level no lower than 2 V, low level no higher than 0.4 V, duty cycle between 10% and 90%, and both positive and negative pulse width no shorter than 80 ns. When the external clock fails at logic high or low, the LM73605-Q1/6-Q1 switches at the frequency programmed by the RT resistor after a time-out period. TI recommends connecting a resistor to the RT pin such that the internal oscillator frequency is the same as the external clock frequency. This allows the regulator to continue operating at approximately the same switching frequency if the external clock fails with the same control loop behavior. Refer section 7.3.9 in the datasheet

    Time out period will depend on the frequency of the external clock, the important thing is to maintain the duty cycle of the external clock that should be within the 10%-90% range. Example, for 500KHz switching cycle, 90% of a time period (i.e. 1.8us) will be the timeout period. 

    I hope this helps.

    Please close the thread if you think your question has been answered.

    Best Regards,

    Ankit Gupta

    Application Engineer