• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Answers 1 answer
  • Subscribers 64 subscribers
  • Views 559 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TLV703: output peak voltage

Wesley Huang
Expert 1030 points
Part Number: TLV703
Other Parts Discussed in Thread: LP3992,

Hi Team,

  •  The circuit system block diagram is as follows. The output waveform of TLV703 produces periodic 2.64V output peak voltage with an interval of 204.5ms. However, when we use LP3992 of Low-Power semi, this problem does not appear. The LDO output waveform and the schematic is shown below：
  • The enlarged peak voltage is shown below：

          

  •  After checking the input voltage waveform of LDO, it is found that there is no big burr and noise, and the waveform is shown as follows.

             

  •  After that, I grabbed the waveform of WiFi SOC, and found that there would be periodic load current changes. The current change is about 150mA, and the reversed current waveform is shown as follows.

             

  •  So now I preliminarily locate that the peak voltage is caused by too slow transient response, and prepare to connect another 4.7uf capacitor in parallel at the output terminal.
  1. Are my analysis and improvement measures correct?
  2. Are there any better suggestions for improvement?
  3. What do you think is the source of the peak voltage?

 

 

Best regards

Zhihong Huangs

  • 0
    Expert 1030 points

    Hi Team,

    After I added the output capacitor to 10uf, 14.7uf and 22uf,  the output peak voltage is still not decreased which is  around 2.58V.

    Best regards 

    Wesley Huang

  • 0 in reply to Wesley Huang
    TI__Mastermind 45070 points

    Hi Wesley,

    This looks like the load transient response. See figure 14 from the datasheet:

    The output spike you see from the high load current to low load current in the above image verse your application could be due to the difference in the parasitic inductance in the layout. 

    The difference between the two devices could simply be the load transient response capabilities inherent in the design of the different devices. 

    I hope this helps.

  • 0 in reply to Wesley Huang
    TI__Mastermind 45070 points

    Hi Wesley,

    This looks like the load transient response. See figure 14 from the datasheet:

    The output spike you see from the high load current to low load current in the above image verse your application could be due to the difference in the parasitic inductance in the layout. 

    The difference between the two devices could simply be the load transient response capabilities inherent in the design of the different devices. 

    I hope this helps.

  • 0 in reply to JCHK
    Expert 1030 points

    Hi John,

     Thanks for your reply.

    Best regards 

    Wesley Huang