TPS62148: VOS pin "sufficiently high voltage ripple"

Hi Darren,

I am unable to find any specific information on ripple voltage value at the output for proper operation. The designs are usually done with a specific range  on the inductor and output capacitor as mentioned on page 14 of datasheet. Another way to look at this could be through stability and that adding too much cap (lower ripple) and or too less cap (higher ripple) can lead to significant movement of the double LC pole which might be hard to compensate internally with the DCS control architecture. This app note (https://www.ti.com/lit/an/slva463a/slva463a.pdf) explains effects of increasing or decreasing the L and C which is at the direct output of the IC - the app note uses TPS62130 and family of devices but this analysis should be similar for any device with DCS control scheme. In addition, best way to ensure a stable design would be to do loop respnse measurements on bench with the other loads and PCB parasitics in order to ensure those effects are captured when checking stability. 

Let me know if this helps. If you have other specific questions on your design and its application, please let us know.

Regards,

Amod

I think to truly answer this question, I need to understand how the DCS-architecture regulates based on output voltage ripple, because of this comment:

Because the DCS-Control™ architecture is fundamentally hysteretic and thus regulates based on output voltage ripple...
Taken from: http://www.ti.com/lit/an/slva465a/slva465a.pdf under Figure 3

This Texas Instruments Patent seems to be talking about such a DCS-architecture: 
https://patentimages.storage.googleapis.com/60/45/83/c736b6718d4059/US6147478A.pdf

Figures 4~8 show different implementations of the DCS-architecture...and Equation (4) looks like what is seen in the datasheet, so I am assuming Figure 5 is the best representation. The "VOS" node seems to be connected to the FB node however...

I don't have the time/energy to really delve into this, but from the patent, it basically states this setup controls switching frequency according to this ramp signal generated by R1 and C1, as opposed to relying on the output capacitor/inductor characteristics.

By proper selection of the values of R1 and C1, an amplitude of the additional ramp signal may be obtained that is greater than the output ripple at VOW of the converter 58. As the result, the sWitching frequency of the sWitches S1 and S2 of the converter 58 is increased, While the output ripple is loWered.

Is there any numerical value on an output voltage ripple range you could recommend?
Example: For 12Vin 1.2Vout setup, Figure 35 shows 50mV @ 200mA -> 15mV @ 1.8A
Other figures show as low as around 6mV ripple.
Is it safe to assume ripple needs to be > a few mV?

Darren,

That datasheet discussion really covers an extreme case, not a normal application.  What is driving your question?  can you tell us about your application?  How much output capacitance are you trying to support?

Hi John,

The engineer is really wanting to know how big they can make the output capacitor to reduce ripple as much as possible, while still keeping the device in a proper operating range for line/load transients. The output isn't connected to many loads, but there will still be a massive capacitance here. (They are okay with larger caps and higher footprints for this application)

a) What happens if L and Cout is so high the output is basically DC? 0mV output ripple?

b) The app note here, in Table 1 gives some examples for LC. If the output capacitance is too high for a given inductance, then the LC corner frequency drops, and the circuit becomes unstable...From the graph, it looks like if the Inductor/Capacitor are chosen to give a corner frequency of between 11kHz~50kHz, there shouldn't be an issue, correct?

c)  You want to choose a capacitor with the lowest impedance at the switching frequency for lowest output ripple...right?

d) What does "unstable" for DCS-Control devices mean? Problems with line/load transients, and output voltage dropping or rising?

I hope this helps clarify what the engineer is asking...The engineer is really needing an answer ASAP, so I guess if we could solidify the max output capacitance, that should take care of this.

Regards,

Darren