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TPS650250: TPS650250

Part Number: TPS650250
Other Parts Discussed in Thread: TPS65023


In my design Im not using PWRFAIL _SNS and PWRFAIL pins. Can i keep these unused pins open?

  • Hi,

    I have forwarded your request to Applications Engineer supporting this device.. He is in US time zone and he will provide you the feedback by today or latest tomorrow.



  • Yes, you can leave both the PWRFAIL_SNS and PWRFAIL pins floating (NC).

    PWRFAIL_SNS is a Hi-Z input into a comparator.

    PWRFAIL is an open-drain output. The FET will be on (pulling low) but there is no voltage source so it will not consume current.

  • Any pull up to EN_DCDC1 is required if Im connecting Power good on another regulator to this pin?

  • If PWRFAILz (output) is used, it requires a pull-up resistor to an I/O voltage (1.8V or 3.3V) because it is open-drain.

    If PWRFAIL_SNS (input) is used, it typically requires a resistor divider so the measured voltage goes above the 1.0V threshold when the input voltage exceeds a different threshold. For example, if you were monitoring VIO = 3.3V, you may calculate a resistor divider such that:

    • When VIO = 3.0V, VPWRFAIL_SNS = 1.0V --> VPWRFAIL_SNS = VIO * R1/(R1+R2) --> R2 = R1*((VIO / VPWRFAIL_SNS) - 1)
      • If R1 = 100k, then R2 = 200k

    The exception would be if you are measuring VCORE = 1.1V, you can connect VCORE directly to VPWRFAIL_SNS or with an RC delay added to delay when the 1.0V threshold is crossed for the comparator (which delays the PWRFAILz output signal.

  • In my design, DCDC1 output voltage is 1V. How can I enable EN_DCDC2? 

    Can i use PWRFAIL pin to enable EN_DCDC2? 

  • If you refer to this App Note: Power Supply Design for NXP i.MX 7 Using the TPS65023

    It is using a similar part (TPS65023) with an analog sequencing circuit.

    In your case, you want DCDC1 to be enabled first (VIN connected directly or through a Schottky diode to DCDC1_EN).

    However, if you generate exactly 1.0V it may not be enough to trip the PWR_FAIL_SNS comparator. Also, the PWR_FAILz output is commonly used to release the PORz input of the SoC that is being powered.

    My recommendation for enabling DCDC2 would be to:

    Connect VIN to EN_DCDC2 through an RC delay --> VIN connects to resistor (100kOhm), and the opposite side of the resistor connects to a capacitor (0.1uF ) that needs to be charged before the EN_DCDC2 pin "sees" a high logic level (VIH). R*C = (100kOhm)*(1uF) = 10ms, but with VIN =5V*63% = 3.15V the voltage at EN_DCDC2 will be greater than VIH in <10ms.

    This way, DCDC1 is enabled first by VIN and DCDC2 is also enabled by VIN after a delay, which will allow DCDC1 time to reach the target output voltage (1.0V) and stabilize before DCDC2 begins to turn on.