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TPS54328: Strange SW node voltage waveform

Shawn_Wang
Expert 3811 points
Part Number: TPS54328

Hi team

My customer using the TPS54328 as the 16V to 4V function, the input is the four-cell Li-battery and the fully-charged battery voltage is about 16.4V, the load is a GPRS module in which the startup current can reach up to 2A and the working current is less than 1A.

The question is that the SW node voltage waveform looks a little strange, but the output 4V rail looks stable. I am not sure if it is an expected SW waveform. Could you please tell me under what circumstances would the SW voltage waveform look like this? I want to check whether the customer's circuit is well-designed. The SW detail please refer to the following photos.

  • 0
    TI__Mastermind 30800 points

    Hi,

    Can you please tell me what is the load current and VOUT when it does this? It will be good to plot inductor current as well to see if the device is going into Auto-Skip Eco-Mode. Also, increase the load and see if there are any changes on the plots. The SW zoomed in look on and switching to 10V if I read that right. if you send me the SCH i can review it as well. 

     

    Thanks!

    Tahar

  • 0
    TI__Mastermind 30800 points

    Here is my comment of the SCH. Shawn W is working with me on this offline.   I WILL CLOSE THIS AND WORK THIS ISSUE THRU EMAILS going froward.  

    SCH:

    • For sure the caps need to be rated properly.
    • The CIN cap recommendation is a ceramic capacitor from 10 µF to 22uF for the decoupling capacitor and an additional 0.1-µF capacitor from VIN to ground to improve the stability of the over-current limit function. The capacitor voltage rating for 16V input, I would put at least 20% margin on the Voltage rating from the max expected VIN.
    • Bootstrap Capacitor looks good
    • VREG looks good, just make sure the voltage rating is OK as well
    • LC filter, 3.3uH is good, but I would reduce the output cap to 22uF to 68uF. Otherwise, you may create stability issues. The peak current for the chosen inductor need to be meet the at least 20% more the desired Ipp. Use equation 6 and 7 in the datasheet to calculate the peak current.
    • The feedback resistors for 4.0V looks ok.
    • The soft start cap they choose will give a long start time. Please verify what they want as soft start using equation 2 in the datasheet.

     

    The layout for these devices is as important as SCH, I would look into these point as well:

     

    • Make sure switching current loop as small as possible by keeping the SW node as physically small and short as possible. Do not allow switching current to flow under the device. Exposed pad of device must be connected to PGND with solder.
    • Noise free traces of the analog and non-switching components, keep them well shielded and away from switching components.
    • Place VREG5 capacitor near to the device, and connected PGND. The same with Voltage feedback loop must be as short as possible, and shielded.
    • Connect COUT to a broad pattern of the PGND.
    • CIN capacitor must be placed as near as possible to the device
    • Very important to make a single point connection from the signal ground to power ground. Otherwise, the signal ground will pick up all the noise and will make the device nonfunctional. See datasheet example layout.

     

    Please make these changes and test again. Also, I would test across load to make sure the issue is covered across load.

    Some comments about the tests:

    • I would probe the input voltage as close as possible to the pin of the device, to make sure that the battery and the connection are good and not causing any drop or something along this line.
    • The SW plots you provided, the signal itself looks clean, but after few SW cycles, both HSFET and LSFET turns off. I wonder what happen to VOUT at that time. probing VOUT will help as well.
    • Even further testing that can be done is taking stability test after fixing the SCH per my comments above.