TLV62090: Output voltage drop

Hi Shin,

I will be looking into your request. 

Have you tried to adjust the feedback resistors. Sometimes there are more losses depending on the type of resistors used. This could be the simplest way out.

What is the maximum load for the application?

Could you please share the layout? An improper layout can also lead to more losses.

Regards,

Febin

Hi Febin,

Thank you for your reply.

Hi Shin,

I would like to get some more clarifications regarding this issue.

-Do you observe a lower output voltage (0.94V) even at a lower load (like 2A)? Or was this observed only at 3A?

-The schematic looks fine and I don't see any issue in Vout regulation when PG is connected. Could you try a 500k pull-up resistor at PG pin instead of 20k? Please check if you have a better regulation.

-Can you provide a complete schematic of your application. Where is the +1.0V_A_PG connected to? It does not look like the PG is connected to the Vout directly.

-What kind of PG circuit did you mean? It is usually a direct connection from the PG to the second device. I did not understand your requirement.

Regards,

Febin

Hi Febin,

Answers :

    1. It is independent of the load current.

     2. When using a 100k pull-up resistro on the PG pin, the PG signal did not work properly.

     3. The FPGA and MAC devices receive the PG signal to check the 1.0V power status. Since the devices use a 3.3V power, so I connected the 3.3V pull-up to the PG pin.

     4. When the voltage levels of VOUT and PG are different, Please check if the circuit design is correct.

I confirmed that the VOUT drop occurs when the pin status of the second device connected to the PG pin is unstable.

I can not figure out why the PG pin affects the VOUT level. Please explain in what case the symptom may occur.

Regards,

JH

Hi Shin,

Could you please share a complete schematic and layout?

I think you are connecting the PG signal to the Vout of the same device.This is probably causing the error. Please share the measurement plots for PG and Vout of the same device.

Regards,

Febin

Hi Febin,

Can I share the complete schematic and layout by email (jh.shin@arrow.com) ?

The PG pin is an open drain output and the only recommendation is "The pull-up resistor cannot be connected to any voltage higher than the input voltage of the device".

I can not understand that the cause of the issue is not connected to PG signal and the VOUT of the device.

Please explain in detail.

Thanks a lot and Regards,

JH