TPS650250: Voltage detector comparator propagation delay

Uchikoshi-san,

Are you testing on the TPS650250 EVM (TPS650250EVM-447) or are you testing the IC on a PCB built by the customer?

If you are testing on the customer's PCB, please share the schematic of the design showing the PMIC device and external components.

I agree that this behavior does not appear to agree with the datasheet. Looking at the datasheet, it indicates that there is a direct connection between the PWRFAIL _SNS comparator input pin and the PWRFAILz open-drain output pin. My understanding is that this is an all-analog design and there is no digital core that would deliberately introduce a delay in between the comparator and the transistor.

On your oscilloscope captures, I actually cannot see the voltage on the "+1.1V" DCDCx output (shown on Channel 3 in Pink). The datasheet does specify clearly that the Rising edge of the PWRFAIL_SNS comparator would have to be 1.0V*(1 + 0.02) + 60mV + 25mV = 1.105V worst-case to overcome hysteresis and "overdrive" to effectively switch the comparator from a low-to-high state at the output.

Since I cannot see this value in your measurements, I wonder if the "+1.1V" output is at a high enough voltage to guarantee the comparator changes state.

Typically, if we add a delay on purpose using a digital core and integrated logic, the delay time is much longer (20ms or 100ms) after the rising edge of the input signal. Also, propagation delay implies that analog circuitry is used instead of digital clocking or de-glitch filtering.