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TPS62148: 100% Duty-Cycle

Darren (FAE)
Expert 5483 points
Part Number: TPS62148

I was hoping for some help regarding the 100% duty-cycle operation of the TPS62148 for 5V output.

1) Figure 80 from the DS shows around 700kHz switching frequency before the graph ceases (device enters 100% duty-cycle mode?)
- This is about 1.5us period. The Duty cycle (per 9.4.3 from DS) is VOUT/VIN, so at 5.3V, would be 94%. The off time is then around 80ns.

From the DS, this is the value given for minimum off-time.

Thus, any input voltage lower than this will cause the device to operate in 100% duty-cycle mode, correct?

2) The DS states:
The high-side switch stays turned on as long as the output voltage is below the internal set point.
What is the internal set point? Is this the output voltage set-point with the FB resistors? In other words, at 100% duty-cycle, if the input voltage increases, the output voltage will increase, and if the output voltage goes higher than the "set" output voltage, switching operation begins again?


3) As Vin decreases, switching frequency decreases...until duty cycle is high enough that the minimum off-time of 80ns is met, and the device enters 100% duty-cycle mode. Once in this 100% duty-cycle mode, can it withstand long-periods of time in this operation?

4) Is there a way to calculate the switching frequency as it decreases related to lower input voltage? Equations 3) and 4) are for TON time given a set, non-changing switching frequency, so I was wondering how the Figure 80 frequency could be calculated...?

Regards,

Darren

  • 0
    TI__Mastermind 21795 points

    Hi Darren,

    1. Yes that interpretation is correct. In reality, due to losses, the duty cycle will be higher than the ideal equation given in datasheet. So, for higher currents where losses are higher, the device will enter 100% duty cycle mode at a higher Vin compared to lower current situations. You can also predict this using eq.7 in datasheet.

    2. That is correct. 

    3. No limitation that I know of to sustain long periods as long as junction temperature limit is not violated. At 25C, the loss during 100% duty cycle operation does not seem very high even at highest output current.

    4. One could make a basic model for PWM operation with the on-time equation in datasheet - eq 1 and 2. Eqs. 3 and 4 are when AEE is employed and that is typically at lower Vout's. But there could be other factors like on-resistance variation with losses, exact loss estimation, precise time constants for on-time equation, etc. that will make it hard to match the 100% duty cycle decrease in frequency.

    Please let me know if you have any other questions.

    Regards,

    Amod

  • 0 in reply to Amod Vaze
    TI__Expert 5483 points

    Thanks for the reply; just what I needed to know :)

    -Darren