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TPS65916: ACT2OFF Sequences for TPS659162 + AM5718-HIREL

Part Number: TPS65916
Other Parts Discussed in Thread: AM5718, TPS22965, , AM5718-HIREL


I would like to ask about the power-off(ACT2OFF) sequence of the circuit that combines the TPS659162, AM5718, and TPS22965.

-Refer to the user guide's(SLVUAO4D(TPS65916 User’s Guide to Power AM571x)) configuration shown in Figure 1 and build the circuit configuration.
-Connect load switch (TPS22965) output to VIO_IN (TPS659162) and vddshv1-9 (AM5718).

If the external DCDC + 3.3V (TPS54335 in Fig. 1) falls at almost the same time as GPIO_5 (POWERHOLD) goes LOW,
Isn't the power-off sequence requirement of AM5718 not met? (SPRS999(AM5718-HIREL Sitara™ Processors Silicon Revision 2.0) p.180 Figure 5-3)
(Before porz becomes Low, the output voltage of the load switch drops and vddshv1-9 fall.)

Are there any countermeasures?

Best Regards,


  • Hello,

    In this case I would not be concerned about breaking the power down sequence. The sequencing used in this design was validated with the AM571x team at the time of release.

    From a technical standpoint, as soon as the RESET_OUT pin of the PMIC goes low, the processor goes into a RESET state. While GPIO_0 goes low at the same time as RESET_OUT, the external device (in this case TPS22965) will take some additional amount of time to turn off after it is disabled. In addition to this, the output capacitance on the rail will cause the voltage to decay over time. Both of these factors will cause the rails supplied by TPS22965 to go low near the same time as given in the AM571x datasheet. 

    Best regards,

    Layne J

  • Hi Layne J,

    Thank you for your prompt reply.

    Looking at your reply, I understand, but please tell me two things.

    How long does it take for the PMIC to output RESET_OUT after the reset signal (LOW) is input to GPIO_5 (POWERHOLD) of the PMIC?

    If DCDC has output discharge function or other components are connected between DCDC3.3V and LoadSwich input and it consumes a lot of current, the output voltage of LoadSwich will drop immediately.
    In this case, after the reset signal (LOW) is input to GPIO_5 (POWER HOLD) of PMIC, the output voltage of Load Swich has dropped while PMIC outputs RESET_OUT.
    Isn't it possible to keep the power-off sequence requirement?
    Best Regards,

  • Hello,

    See my answers for your questions below. 

    1. Please refer to figure 5-5 found on page 37 of the TPS65916 datasheet. This figure shows that RESET_OUT will go low with no delay after POWERHOLD goes low. (I attempted to post a screenshot but it does not appear to be posting correctly, my apologies.)

    2. As I mentioned above, this sequencing was validated to work according to the AM571x team and they have confirmed this OTP will not cause any issues when used according to the TPS65916 User’s Guide to Power AM571x. I would recommend reaching out to the processor team if you have further concerns about the timing of that rail, they will be able to provide better reasoning as to why they approved the sequencing and what level of flexibility is allowed in the sequencing on the datasheet.

    Best regards, 

    Layne J