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CSD95379Q3M: Reverse conduction, as in connecting to negative.

Part Number: CSD95379Q3M

I have made a full bridge using 2 of the mentioned CSD95379Q3MT part. The plan is to connect to ground at one side. Use PWM on the other side to generate a sine wave. Then reverse for alternating voltage. 

This appeared to be possible according to datashet by using FCCM. As in setting pint 1 (SKIP#) to HIGH, and PWM to low. However using a fluke ohmmeter (+ at VSW and - at PGND), I never get anything but an OL reading doing this. With SKIP# to LOW and PWM to high I can easily verify the FET turns on using fluke (+ at VIN and - at VSW). VIN is not powered while testing. Only setting VDD at 5V. 

This test is done using a custom protoype board. (Actual PWM also appears to fail, so went back for slow DC readings).

Did I misinterpret the datasheet?

See below used schematics for one of the half bridges:

PhaseAPWM and PhaseASwitchMode are directly connected to MCU outputs ranging from 0 and 3.3V. 

  • Hi Majolillo,

    Thank you for your interest in  CSD95379Q3MT.

    I am not very clear about your connection for the full bridge, could you please attach the schematic for the whole circuit (full bridge)?

    If I understand correctly, the low side FET (between VSW and PGND) supposes to be turned on if #Skip=high, PWM=low, with VDD=5V. When PWM is high, the high-side FET (between VIN and VSW) is turned on no matter #SKIP=high or low. When SKIP=tri-state, both high-side and low-side FETs are turned off. Could you please confirm the FET you measured accordingly?

    Thanks,

    Qingquan 

  • Qingquan Tang said:

    Hi Majolillo,

    Thank you for your interest in  CSD95379Q3MT.

    I am not very clear about your connection for the full bridge, could you please attach the schematic for the whole circuit (full bridge)?

    If I understand correctly, the low side FET (between VSW and PGND) supposes to be turned on if #Skip=high, PWM=low, with VDD=5V. When PWM is high, the high-side FET (between VIN and VSW) is turned on no matter #SKIP=high or low. When SKIP=tri-state, both high-side and low-side FETs are turned off. Could you please confirm the FET you measured accordingly?

    Thanks,

    Qingquan 

    Inserting rest of the full bridge. I am only testing 1 half bridge at the time however, so the rest should not matter.

    The schematics above presents my 2 probe areas, while I am manipulating PhaseAPWM and PhaseASwitchMode with either 0, 3.3V or floating.

    1) Setting Skip# (PhaseASwitchMode in schematics) to 0, the circuit behaves as expected. Purple resistance probe conducts well with high PWM (PhaseAPwm in schematic), and Red resistance probe does not conduct ever, as it is emulating a diode. 

    2) Setting Skip# to 3.3V Neither red nor purple probes conducts either with PWM high nor PWM low. 

    3) Noticed a warning in datasheet page 9, that one should not "start driver" with Skip# in tri-state. Attempted forcing Skip# to both 0 and 3.3V at startup. Same result as in scenario #2. Unsure what start driver means. If that means setting PWM high, or powering VDD?

    4) Found a reference design using this chip. Noticed that Skip# is set to VDD, as in 5V instead of 3.3V (or anything above 2.65V as per datasheet page 5). Same result as in #2.

    5) Combined scenario #3 and #4. Forcing Skip# to 5V at startup. Now the IC works as expected. Purple conducts with PWM high, and red conducts with PWM low. 

    So far everything have been done with hard jumpers. With this info however, I could redesign my PCB to only power VDD after setting Skip#s to 5V before proceeding. Does this mean that the datasheet is incorrect with respect to logic levels? Setting 5V from MCU requires another transistor, so hopefully there is another way?

  • majolillo said:

    5) Combined scenario #3 and #4. Forcing Skip# to 5V at startup. Now the IC works as expected. Purple conducts with PWM high, and red conducts with PWM low. 

    So far everything have been done with hard jumpers. With this info however, I could redesign my PCB to only power VDD after setting Skip#s to 5V before proceeding. Does this mean that the datasheet is incorrect with respect to logic levels? Setting 5V from MCU requires another transistor, so hopefully there is another way?

    Update with more tests.

    6) Tested forcing Skip# to 5V (VDD) at startup, and then changing to 0V for diode emulation. Then I can no longer go back to forced conduction by switching Skip# back to 5V. (Purple nor Red ever conducts)

    7) Forcing Skip# to 0V also appears to take away the possibility of ever going back to forced conduction.

    My conclusion is that Skip# can only be programmed in hardware once, and never changed (or possibly with a VDD reboot). Is my conclusion correct?

  • Hi Majilillo,

    Thank you for the full schematic and all the details. Now I understand you are still testing one power stage which is basically half-bridge setup.

    One question though when I look at your step 4 and step 5, I didn't understand the difference in setup but came out with different results?

    About your question, usually "start the driver" means VDD start up. Do you have a VDD bypass cap very close to the VDD pin? I didn't see it in the schematic. We will need 1~2uf between VDD and GND to prevent glitch on VDD voltage.

    The SKIP# is an input signal pin to tell the power stage to get into FCCM, DEM, or low power state, but the power stage itself will detect the VSW voltage (zero crossing detection works here) to make the final decision. To complete the validation, I think you may still want to power the circuit up to see if the operation is correct or not. Of cause you will need to make sure no short circuit on the board before powering up.

    If you still have issues, you may send me further questions and test waveforms to q-tang1@ti.com. I will try to help.

    Best,

    Qingquan