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UCC21750-Q1: Suggestion of which value of capacitor could be connected to FLT PIN

Benjamin Zhou
Expert 4000 points
Part Number: UCC21750-Q1

Hi Team,

  My customer now is using UCC21750-Q1 for driving their new IGBT module, could you kindly help to suggest which value of capacitor could be connected to FLT pin and GN? 

 Expect for your reply, thanks.

Best Regards

Benjamin

  • 0
    TI__Genius 10652 points

    Benjamin,

    If you are referring to cap value between FLT and GND, customer can use something like ~100pF, though it is not strictly required.

    Recommend to share our EVM schematic with the customer also.

    Please let me know if there any other questions on this.

    Best

    Dimitri

  • 0 in reply to dimitri james
    TI__Expert 4000 points

    Hi Dimitri,

      Actually has provided the schematic and PCB layout files to customer.

      Currently customer used 6 220pF capacitor parallelized, and was warried about would over the current capability of FLT pin and may caused damage,  could you kindly share comments on the FLT pin architecture model which the maximum capacitor could be used?

      Expect for your comments, thanks.

    Best Regards

    Benjamin

  • 0 in reply to Benjamin Zhou
    TI__Genius 10652 points

    Benjamin,

    We don't have a maximum capacitor spec.

    FLT pin is opendrain output. Internally it is an NMOS and drain is connect to pin. (Figure 8.2 of datasheet shown below)

    A larger capacitor than 100pF  is OK, but not too large. The smaller 100pF current discharged rather quickly, but for a larger and larger cap there is increased potential to damage the NMOS for FLT/RDY because the "peak" current when discharged becomes more like a large DC current. Other important is to make sure not to use a really low Pullup resistor because Abs. Max condition for current into RDY/FLT is 20mA

    I think 6x220pF would probably be fine, but I would rather recommend the customer to reduce it, just use one or two at most. From my perspective there is really no need for such a large capacitance. And it will slow down the fLT/RDY signal a lot by RC delay, which to me has no benefit.

    If possible, recommend the customer to just populate 1 or 2 caps at most, but even if not there there should not be any harm to the device.

    Additional information on FLT/RDY internal NMOS spec is located in the datasheet here and copied below.

    https://www.ti.com/lit/ds/symlink/ucc21750.pdf#page=10

    Any additional questions, please let me know.

    Best

    Dimitri