• State TI Thinks Resolved
  • Locked Locked
  • Replies 5 replies
  • Answers 1 answer
  • Subscribers 64 subscribers
  • Views 244 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

UC3853: UC3853 | PFC Loop Design

Subrahmanyam V
Intellectual 480 points
Part Number: UC3853

Hi!

I have a small query in PFC compensation implementation.

I understand that we have to consider the worst case conditions (low-line and full load) while designing any loop compensation.

But why is that the low-line of PFC is considered as the peak of the minimum voltage specification, when the input voltage varies as a sinusoid and has a zero-crossing?

How can one justify using the Vmin,peak for designing the outer loop compensation?

Can someone help me understand on this topic?

Regards,

Siri

  • 0
    TI__Mastermind 34465 points

    Hello Siri,

    PFC compensation loops are very slow and are designed to have a bandwidth of one tenth or so of the minimum operating frequency.
    This is because the output is a DC voltage and you cannot have a situation where the output is responding to the normal variation in the AC input.
    Loop compensation has to track a fixed value of the input.
    This simplification also makes it easier to analyse the pfc loop.
    For stability purposes the peak input is the worst case situation because a small error in the pwm here will cause a relatively large error in the output.
    For the pfc you would normally evaluate the loop response at high line and also low line with a maximum load on the output.

    Regards

    John

  • 0 in reply to John Griffin1
    Intellectual 480 points

    Hi John,

    I understood the points you mentioned. My query is;

    suppose I consider universal input voltage range of 85-265 V

    I would consider the worst case low line as 85*sqrt(2) for designing the voltage loop.

    Why dont we consider any value less than that as the input can go to 0 also?

    Regards,

    Siri

  • 0 in reply to Subrahmanyam V
    TI__Mastermind 34465 points

    Siri,

    Why do you think the worst case case situation for loop stability is the low line ?

    Regards

    John

  • 0 in reply to John Griffin1
    Intellectual 480 points

    Hi John,

    For any converter, I understand that the gain depends on the input voltage and hence if I make sure that the there is sufficient GM and PM at the low line and full load, my converter would be definitely more stable at higher voltages.

    Hence, as the worst case, I would consider the low line.

    But in PFC, if I consider the power balance and do small signal analysis, I understand we get the low line voltage as sqrt(2)*vrms.

    But, why isn't some kind of instability kicking in when the input voltage varies below this minimum peak value!

    Kindly correct me if my understanding is mismatching from yours.

    Thanks,

    Siri

  • 0 in reply to Subrahmanyam V
    TI__Mastermind 34465 points

    Hello Siri,
    Issues with stability in feedback systems are usually discovered at the peak input voltage.
    This is probably because the loop gain is highest here and overall phase margin is worst case as the gain rolls off.
    The pfc is a dynamic system and you will have to check it at a fixed dc input.
    This is just the nature of the Bode plot.
    For completeness of testing and to assure yourself the system is stable you should test at both high line and low line.
    For analysis purposes you would need to do you simulation at high line


    Regards

    John