I have a project use TPS23750 and found some issues. . Attached is the schematic diagram. I use 23750 to generate 5V voltage for my system. But now the output is only about 2V. Which change I can do for this issue?
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I add 30V voltage to vdd-vss, and the output is normal about 5V. But the input current is about 115mA, and our 5V load only needs 50mA . The inductance and capacitance at the load end will heat up. Vgate switches one group every 500ms. When vdd-vss is increased to 35-40v, it will crash. The current drops to 30 ma.
The secondary has a 33uH inductance. Typically for flyback it is only in the 100nH range. The 33uH is probably making this converter unstable.
I might be good to order the TPS23750 Flyback EVM and compare your solution since the EVM is working solution.
4.7uH is still much larger than the 100nH range. Please change it to 100nH range.
As for the UVLO, the input voltage is between 42-57 volts typically. The rising UVLO threshold for the standard is 39.0V. That means the IC is going to try to turn on at a voltage greater than or equal to 39V. This supports the PoE standard input range of 42-57.
The UVLO falling threshold is 30.5V. When VDD_RTN reaches 30.5V, the IC will shut off. Until that point, the IC is still trying to be powered. So if there is a 48V input the IC will be powered. Then when it is removed, the IC will continue to switch until the VDD_RTN voltage drops across 30.5V.
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