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CSD88584Q5DC: CSD88584Q5DC RC Thermal Model

Part Number: CSD88584Q5DC
Other Parts Discussed in Thread: TIDA-00774, TIDA-01516, DRV8306

Are R-C thermal models available for the CSD88584Q5DC part? Ideally, I'd like a model for junction to case as well as junction to ambient.

Thank you!

  • Hi Jim,

    Thanks for your interest in TI FET products. Unfortunately, we do not have any RC thermal models available for this power block device. Values for RthetaJC and RthetaJA are specified in the datasheet. I am also including links to blogs explaining how TI specs thermal impedance for our MOSFETs and a technical article on how much power can be dissipated in our FET packages. This is a dual cool package capable of topside cooling with a heatsink which can greatly improve the thermals for this power block. Can you share information about your application? Is this being used for motor drive? This power block has been used in many motor drive EVMs and reference designs. You can find detailed information under the Design & development tab in the product folder on

  • Hi John,

    Thanks for the quick response. I am pretty familiar with thermal impedance, but in order to determine junction temperature of transient power (non-square pulses), I have needed to use thermal R-C models to simulate and determine the junction temperature. For example, in my application, I have a transient 90 A current that decays (during braking of a motor) over about 10-12 seconds, with the majority of the decay occurring in under 6 seconds.

    Is this the wrong approach for transients?



  • Hi Jim,

    Normally, I would use transient thermal impedance curves to estimate the junction temperature rise. However, TI only provides those curves for single, discrete FETs. I pulled up the characterization data for the CSD88584Q5DC and it includes Zthjc and Zthja curves. I have contacted a colleague to make sure I am interpreting these curves correctly and to see if this will help you out.

    Additionally, Figure 7 in the datasheet shows single pulse current vs. pulse duration for maximum RthetaJA of 125degC/W. This curve only goes out to 1 second duration where the maximum pulse current is just over 50A. The only condition given for this curve is TJ = 25degC and I believe this is without a heatsink or any airflow on the minimum pad area as shown on page 5 of the datasheet. I think the capability in your application should be better. Obviously, this is going to be very dependent on your actual PCB layout and stackup and whether or not you're using a heatsink and have any airflow. The only thing that TI can control is RthetaJC as this is dependent on the die size and package design.

    I'll get back to you as soon as I have more information.

  • Hi Jim,

    I'm still working to get your answers. Please standby.

  • Hi Jim,

    I have submitted a request to the packaging team to generate the R-C thermal model for the CSD88584Q5DC. I will let you know when the model is complete. Hoping it won't take too long.

    In the meantime, you should take a look at TIDA-01516 (600W, BLDC motor drive reference design) and TIDA-00774 (1kW, BLDC motor drive reference design). The first one uses a single CSD88584Q5DC per phase and the second one parallels two per phase. These are pretty good examples of the capability of this device in a motor drive application. I am a bit concerned about a 90A peak that decays over several seconds. It's a lot of power dissipation over a fairly long duration of time.

    I'll update you when I get a target date for completion.

  • Hi Jim,

    I haven't forgotten you. I am still waiting on the R-C model from the packaging team. I will update you as soon as it is done. Apologies for the delay.

  • Hi Jim,

    I've gotten some questions back from the packaging team on modeling this device below. Can you provide a more detailed description of the braking operation? For example, when braking, are both FETs on or they PWM'd at some duty cycle? Are you planning to use a heatsink?

    1. We can’t generate RC network with two power sources.  We can only generate RC network with 1 varying source (the other source must be constant).
    2. RC network needs a sink temperature node (temperature node that doesn’t change during the event).  Typically this is air temperature in a JEDEC setup.  This could be the DAP (thermal pad) temperature but this is only true for very short time (ms).  Please discuss this with customer about this constraint.

  • Hi Jim,

    Apologies that this is taking so long to complete. Below is feedback from the engineer working on the R-C thermal model. He does not believe that an R-C model will work for this as explained below. This power block device in dual cool package has two die (heat sources) and two sinks (thermal pads on top and bottom of the package). Please review and let me know how you would like to proceed.

    From TI packaging engineer -

    RC network will not work for this for following reasons:

    1. There are two heat sources and two sinks.  RC model need a single GND node.  I don’t know how to generate RC with multiple sink nodes.
    2. The time customer asked for is too long for RC model.  Under 12s, the temperature behavior will go beyond package so system attribute must be considered.  System includes any top heat sink, PCB design, air flow, etc.….


    We can provide detailed model for customer to run thermal simulation.  Please find out what simulation software customer uses.  We can provide model in Icepak and Flotherm; for other tools, we can provide the 3D cad file together with list of material properties.

  • We are using the DRV8306 in our application with a 360 W motor. As for braking, we are using the nBrake input on the DRV8306, so that controls the low side FETs by turning them all on.

    As for the RC simulation, I have attached a picture of the type of circuit I am looking for. Where I2 is the power dissipated in the FET, V1 is the ambient temperature and the junction temperature is measured where the voltage probe is in the upper left of the circuit. Junction to case or junction to board are sufficient as junction to ambient is highly dependent on our PCB layout.

  • Hi Jim,

    Thanks for the update. I have shared this with the packaging engineer working on the model. I believe having only the bottom FET on helps to simplify the model. Can we further assume most of the heat is being dissipated thru the thermal pad on the bottom of the package and into the PCB? If you're not using a heatsink to remove heat from the top of the package, I think that should be a reasonable assumption.

  • Hi Jim,

    Since we have moved this discussion to regular email, I am going to close out this thread.