This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LMG3410R070: Question about the spice model

Part Number: LMG3410R070

Dear officer,

Hello, we are working on Wireless Power Transfer and we are using your product LMG1025 and trying to add LMG3410R070 in out designs. As we know and also you have mentioned in technical documents of LMG3410R070, the PARASITIC INDUCTANCE in drain and source (including WIREBONDS, interconnects, and package parasitics) of the power transistor are VERY IMPORTANT and will highly affect on the performance and degrade it from what we expect.

I reviewed the SPICE MODEL of LMG3410R070 and no where these inductors are modeled. Also, the parasitic inductors in SUPPLY of the CMOS driver which is realy important. I use EM simulation for extracting PCB parasitics but I don't have any estimation about the parasitics in the package and haven't modeled them.

I was wondering if you could provide me some detailed information about those above mentioned parasitics to have more accurate simulations and be more similar to reality. 

Thank you,




  • Hello Ehsan,

    Thank you for contacting us! Yes you can correct that these inductance numbers are important as they will affect the circuit performance. Since the numbers are not on the datasheet, and we are not able to disclose them. However, for our QFN package with integrated driver, the common source inductance is zero, source and drain inductance is minimized in our package. Compared to the power loop inductance from the PCB, those inductance could be neglected. To simulate, it's sufficient if you add the power loop inductance from PCB to the circuit.

    For the gate drive loop inductance, since our driver is integrated, the gate drive loop inductance is minimized as well, and is far less than the discrete driver solution. We have tested the gate driver performance internally and made sure it will switch reliably. One thing to note is that in the actual PCB layout, the VNEG cap should be close to the pin so no extra gate drive loop inductance will be added.

    If this helps, could you please click "this solves my issue" button. Thanks!


  • Dear Yichi,

    Thank you for your prompt reply, I have minimized the PCB parasitics and also have put high performance Capacitors for decoupling on PCB. But, if I add even 500pH inductance in Source and Drain(especially Source) this will affect the circuit performance. You say put them ZERO but we know that they are not actually Zero. There are always wirebonds parasitics(even if you have put multiple pins) and your package is big and we usually use 1mm wire=700pH as a rule of thumb (and 10 parallel pins wouldn't divide it by 10 because of mutual inductance) . So I think in our application it can not be neglected. 

    I don't understand that you have a product and you are giving WRONG information to customer and say "we can not disclose right information"???!!!! 



  • Hello Ehsan,

    For estimation purposes, you can put 200pH for source and drain inductance for the package. This number is an estimation and the actual inductance in the package could be different.

    Hope this helps.