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LMG3410R070: Fault is always asserted

Part Number: LMG3410R070

I am using 4 LMG3410R070 devices to form a three-level flying capacitor converter.
When I did experiment for a three-level buck configuration with only 100kHz switching frequency, 30% duty cycle, and simply resistor load 125ohm, the fault signal was always asserted if I increase the input voltage more than 100V (at this configuration the voltage across the device will be only half of the input voltage).
Since the load, I was using is very small, it is impossible to be over current, and also the temperature of the device was maintained bellow 35degrees Celcius, so it's not over temperature neither. Therefore, I think the possible reason causing the fault is only UVLO but I am not sure.

For the voltage supply of the integrated driver, I used a 3W isolated dc-dc power supply with 12V output voltage.  And for the bias capacitor of Vdd, I used 1uF MLCC 50V x7R. I also tried to change this bias capacitor to 10uF  MLCC 35V x5R but the result was still the same.

It has been a month I am trying to solve this problem but still, I can't figure it out the cause of the fault signal is asserted.

Thank you in advance.

  • Hello Fiqih,

    Thank you for contacting us! Based on your description, I tend to agree with you that it most likely to be device UVLO.

    Here are a couple questions in order to better help you:

    1. Did you try this scenario with no load? Did you see fault triggering at 100V?
    2. In the circuit you designed, are you able to see which FET has fault? If not, are you able to probe the fault pin? You will need differential probe for high side signals.
    3. Could you also probe the Vneg and BBSW pin? Vneg is the voltage that will trigger the UVLO.
    4. Also could you share your schematics? We can take a look and see any potential problems.

    Regards,

  • Dear Yichi Zhang,

    Here is the answer to your questions;
    1. Did you try this scenario with no load? Did you see fault triggering at 100V?
      Yes, I tried it. But it was even worse at no load, the fault is triggered at around 70V. This is probably caused by the unbalance voltage of the flying capacitor since at no load there is no resistive load to help the flying capacitor reach the balanced voltage.
      And I also forget to tell you, if I increase the frequency the input voltage triggering the fault signal will be lower, e.g. at 1 MHz switching frequency the maximum input voltage before the fault signal is asserted only around 50V.
    2. In the circuit you designed, are you able to see which FET has fault? If not, are you able to probe the fault pin? You will need differential probe for high side signals.
      Yes, I can check every single fault signal from each device but I need to modify my program tho. Before, if I am not mistaken the first FET had fault was Gan2 (you can see the schematic attached bellow) and after that, probably due to imbalance operation all the FETs had the fault.
    3. Could you also probe the Vneg and BBSW pin? Vneg is the voltage that will trigger the UVLO.
      Yes, I can. I will check it later when I have access to my lab. Due to this pandemic, the time for the experiment in the campus is limited.
    4. Also could you share your schematics? We can take a look and see any potential problems.
      I attach the schematic bellow.

    FCMI - Project.pdf

    Thank you very much. Hopefully, my answers can help you to diagnose my problems.

  • Hello Fiqih,

    Thanks for providing this information to help us identify the cause for the issue you're seeing. We will review this and get back to you in 3-4 business days. 

    Thanks, 

    Arianna Rajabi 

    ti.com/GaN

  • Hello Fiqih,

    From the schematics, could you confirm the value you used for the VNEG capacitor, BBSW inductor, VDD capacitor and Rdrv resistor? Also are the S1-S5 connected with S6-S12?

    Also let us know if you finished collecting the test results discussed previously.

    Regards,

  • Here is the data you asked:

    VNEG Capacitor: 2.2uF

    BBSW Inductor: 22uH

    VDD Capacitor: 1uF

    Rdrv Resistor: 15kOhm

    S1-S5 are connected to S6-S12

    The FET that has the fault is GAN2.

    VDD, VNEG, and BBSW at 70V (no fault)

    VDD, VNEG, BBSW at 100 V (fault)

    if you need anything else, just let me know.

    Thank you very much

  • Here are a couple suggestions based on the schematics and waveform:

    1. In the schematics, there seems to be no filter at IN pin. Since it's critical signal, it's suggested to have 50 ohm and 22pF filter.

    2. You can try to slow down the switching by replace the Rdrv to 50kohm for testing purposes.

    3. You can try to capture the IN pin signal and switch node waveform to see anything could be found there.

    Let me know if the above helps.

    Regards,