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LMZM33606EVM: Overlapping PGND and GND

Part Number: LMZM33606EVM
Other Parts Discussed in Thread: LMZM33606


For LMZM33606 but also mostly any other Power IC from TI it is advised to seperate PGND and GND in the datasheet. Please look at graphic below: For LMZM33606EVM layer 2 is mostly used for PGND (marked green) and bottom layer mostly for GND (marked blue). That means, GND and PGND are overlapping on different layers, which results in some amount of capacitve coupling between PGND and GND. Other TI EVMs are solving this by seperating GND and PGND in areas that are not overlapping. My question is, is it in general okay to have those two layers overlapping? Is there any specific design guideline available from TI on how to design GND and PGND on PCB layout?

  • Hi 

    the bottom GND layer is used as AGND , you can overlapping these two layer PGND and AGND together, take it as PGND. 


  • Hello,

    as far as I understood, AGND is seperated from PGND as there will be quite some switching noise on PGND from the FETs and it should not interfere with AGND sensitive components. Isn't the PGND then coupling into AGND if they are overlapping?


  • Hi:

    yes, your understanding is right. but in EVM layout, the noise current or voltage will not interfere the AGND, because the AGND used single -point ground way to connect the PGND at top layer, there is no way for the noise go to AGND then back to the PGND, so even you changing the bottom layer to PGND, it is still not interfere the AGND . and PGND is not all noisy, the most noisy part of  PGND is  from Module's PGND to input ceramic cap which is at top layer.