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UCC28180EVM-573: Switching Frequency and Phase/Gain Plot Characteristics

Garret Holt
Intellectual 1050 points
Part Number: UCC28180EVM-573
Other Parts Discussed in Thread: UCC28180,

Hi Team,

I am working with a customer who is using UCC28180 in an upcoming power supply design and they are validating the solution using UCC28180EVM-573.

  1. What are the changes that were made in updating the design from Rev A to Rev B?
  2. In this documentation there are several frequencies used to show how the choice of inductance can improve Harmonic Distortion and the choice of ripple current can also affect this.  Frequencies as low as 18 kHz with large inductance used – are there any issues going to higher frequencies (higher than the 120 kHz example)?
  3. There are some phase/gain plots (Section 6.9), can you verify what switching frequency was used for this example?
  1. Is this crossover freq suggested regardless of switching frequency (given the 50 Hz input power)

Thank you!

Garret

  • 0
    TI__Guru 66135 points

    Hello,

    In a 50 Hz line application the rectified line voltage is operating at 100 Hz.  This will show up as 100 Hz ripple on the boost output capacitor.  To keep current distortions to a minimum it is recommended that cross over the voltage loop at (2*fline/2).  For a 50 Hz line this would be 10 Hz.

    The switching frequency by RFEQ.  You are correct the higher the frequency the less distortion on the line current.  So designing for a high switching frequency helps reduce line current distortion.  Typically PFC pre-regulars are designed for 75 kHz to 100 kHz with 20% to 30% inductor ripple current at low line operation. However, in Europe designers per for design for 30% inductor ripple current when the line voltage is at half the regulated boost voltage and the converter is operating at 50% duty cycle.  This is where the inductor ripple current will be at it's maximum.

    Regards,

  • 0 in reply to Mike O'
    TI__Intellectual 1050 points

    Hi MIke,

    Do you see any issues with running at 200 kHz?  The device is capable up to 250 kHz, but I was wondering if you see any issues with this as most applications I have seen only go up to ~130kHz.

    Thanks,


    Garret

  • 0 in reply to Garret Holt
    TI__Guru 66135 points

    Hello Garret,

    When it comes to designing a PFC boost converter.  Generally most designer chose to design under 150 kHz due to EMI testing.  Some designers like to design at 70 kHz, because this puts the second harmonic at a 140 kHz and makes EMI filtering easier.

    You can design your PFC pre-regulator to operate at 200 kHz and the design will have (200kHz/130kHz)*100 = 153% more switching losses compared to the 130 kHz design.

    Regards,

  • 0 in reply to Mike O'
    TI__Intellectual 1050 points

    Thank you Mike, this has been very helpful. We will be going with 120kHz switching for the reasons you mentioned above. Do we have any suggestions for magnetics? We want to stay in continuous mode from 60 – 550 Watts. The peak power is actually 500 Watts for up to 5 seconds.  The average power is probably closer to 100 Watts.

  • 0 in reply to Garret Holt
    TI__Guru 66135 points

    Hello,

    I would think if you design the highest inductor ripple current for 20% that you will stay in CCM mode down to 55W.  You are doing a universal design the highest inductor ripple current happens when the line is at half the output voltage and the converter is operating at 50% duty cycle.  For 120V AC applications the highest ripple current occurs at the peak of low line.

    5 seconds is 300 line cycles so you need to the design to support 500W.  You can use the excel design tool or the Webench design tool to help select the magnetics, bulk capacitor and R and C values to control your power stage of your design.

    /:1230:0]

    Regards,