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Original question:

UCC27200: Broken Issue

UCC27200: Broken Issue

user5339789
Intellectual 590 points
Part Number: UCC27200
Other Parts Discussed in Thread: LM5025

Hello

In July I asked this issue and continuously we tried to improve. We have continued test torepeat over 100 times ON and OFF.

Now recent phenomena is, gate driver have been broken when turned off power supply.

We have looked at UVLO time constant, we recently found NG case above 1mS time constant.Waveforms_200901.pdf

Current setting is R21 = 130kohm and C12 = 1000pF, estimated 10uS we have not found to be reached broken.

We are considering to change more faster or.

Well do you think that does it make sense?  And tell me reason why it has been broken when turned off. 

ACF-PS_00-c_Primary.pdf

regards, Keiichi Takahashi

  • 0
    TI__Prodigy 645 points

    Hi Takahashi-san,

    What's the E2E thread for your July post? We would like to check the previous discussion history first.

    Regards,

    Gangyao

  • 0
    TI__Mastermind 20950 points

    Hello,

    One observation I have is that the controller VCC is dropping faster than the UCC27200 which means the controller PWM outputs which are the driver inputs are dropping in amplitude also. Can you monitor the controller output/driver input waveforms and the driver input waveforms to confirm the driver is responding to the controller during power down. The reason I ask, is that the UCC27200 is a CMOS input which has fairly high threshold voltages.

    Also I see in the UCC27200 plots where the driver is broken that the VDD has a fast rising pulse that is at or maybe above the UCC27200 abs max rating. This VDD spike may be what is damaging the driver. I think it will be important to find out what is causing the VDD high voltage pulse. Can you confirm where the UCC27200 VDD voltage is generated? I would confirm the operating of this bias supply during power down to see what is causing the high pulse.

    Regards,

  • 0 in reply to Richard Herring
    Intellectual 590 points

    Dear 

    Regarding Vcc level, Controller and Gate driver is common supply voltage so, I do not think that problem is these differentiation.

    Let me explain our recent observation. When Shut-down, On Duty is increased by power supply voltage decreased, in the result HS voltage is over 120V therefore gate driver is broken.

    Recently investigated around 100V HS pin when 60% Load PO. ( there are any big trouble when 10 -20% load) Check please pictures of Waveforms.200923.docx

    We would like to know reason why. Are there any experiences to see such as operation?   Can you check such as phenomena using your reference board?

  • 0 in reply to user5339789
    TI__Mastermind 20950 points

    Hello,

    On you observation 1st comment on when HS increased to over 120V and the driver is broken, I looked at the datasheet and although the SW node is rated at abs max rating of 120V the HB has the same rating. HB will be higher than HS by ~VDD minus the boot diode Vf so HB will be beyond the 120V abs max rating.

    I am not sure what you are asking in the following questions. You mention the HS being ~100V with 60% load I assume during the power down sequence. Are you asking why the HS voltage increases during the power down?

    If you are using a TI controller for the active clamp forward, I would post a question on the controller forum listing the controller part number. As the input voltage is falling the duty cycle increases as you have mentioned which in this case the reset voltage may increase to allow the volt-sec balance for the transformer reset. But for more details on this I would post these questions on the controller forum mentioning the controller you are using. They will have more details on behavior expected in this power down event.

    Confirm if this addresses your questions, or you can post additional questions on this thread.

    Regards,

  • 0 in reply to Richard Herring
    Intellectual 590 points

    Dear Richard

    Yes I am asking this is normal behavior that HS voltage increases during power down, due to On duty increases.

    Next can you assume that HS voltage at 100% load increases more compared to case of 60% load?

    If yes HS voltage is exceed 120V possibly. 

    Could you please advice to avoid increasing this during power down?

    We are using LM5025CMTC so let me check anyway. 

    regards, 

  • 0 in reply to user5339789
    TI__Mastermind 20950 points

    Hello,

    Thank you for confirming your concerns. I would encourage you to post these questions on a thread specifying the LM5025 controller since the controller experts can provide better guidance on how to reduce the switch node voltage during power down.

    I would expect the HS voltage to increase in a 100% load condition compared to a 60% load condition due to duty cycle increase and expected higher current in the transformer primary.

    For the advice on reducing voltage during power down, I would pose this question to the controller forum for the LM5025, but it may likely involve changes to the active clamp components or transformer design.

    Confirm if this addresses your questions.

    Regards,

  • 0 in reply to Richard Herring
    Intellectual 590 points

    Dear Richard,

    Thanks you for your message. I understand that there are risks of increasing voltage more at 100% load rather than 60% load.

    Well I would reconfirm, do you think that the behavior of spike generation (over 120V) at 100% load can occur when power-down?
    Does this phenomenon always occur in this circuit?

    Well, I referred your message, do you assume which components should be changed? gate driver itself? or CR?

    I appreciate if you give some hints why you mentioned.

  • 0 in reply to user5339789
    TI__Genius 13445 points

    Hello, 

    Richard is out of office but I may comment meanwhile based on your latest feedback.

    At any load during power down, if you have spike generation exceeding 120V on HB and/or HS, the gate driver IC (UCC27200) will almost certainly fails as this is beyond the recommended operating conditions of the IC and I suggest ensure any spikes limited to the voltage ratings of the IC in Table 6.3 of the UCC27200 datasheet.

    Regards,

    -Mamadou 

  • 0 in reply to Mamadou Diallo
    Intellectual 590 points

    Mamadou

    Thanks reply but we know well abs ratings so we eager to avoid this spike generation. As I mentioned even if 60% load we may observe around 100V spike during power down state. Can you find what cause of this spike, and are there any other solutions to reduce increasing duty? 

    regards, Keiichi Takahashi

  • 0 in reply to user5339789
    TI__Genius 13445 points

    Takahashi,

    VOltage spikes exceeding the abs max on switch node are likely related to fast dv/dt which you may slow by increase resistance on high-side and low-side gates. The second possible way to reduce voltage spikes from the driver standpoint is adding gate to source capacitors to reduce the dv/dt during rising/falling transitions of the MOSFET turn-on/off from Igate / Cgate = dv/dt.

    I do not provide values because this has to be tailored and tuned to your application requirement until the voltage spikes are within the recommended operating conditions.

    The other possible root cause might be PCB layout in which case driver HO and LO are connected to gates through long PCB traces introducing significant stray inductance in gate driver portion. The switch node should also be confined to small loop to limit the effect of parasitic inductance from Vspikes = Lparasitic * di/dt.

    Regards,

    -Mamadou

  • 0 in reply to Mamadou Diallo
    Intellectual 590 points

    Thank you for your quick response.

    Again I think you to know more clearly what's going on.
    Problem is during power down, gate driver reached broken when positive duty increase and voltage also increased, over 120V.

    Let me explain what waveform is;
    Upper picture is a bad case of broken UCC27200.
    We can see Voltage of SW-node exceeded 120V then Gate-driver has been broken-down, and maybe influences, Vdd become to higher for a while.

    Lower picture is a good case of alive Gate-driver.
    It is kept less than 110V so gate-driver was NOT damaged.

    Our understanding of this broken issue, a cause of voltage increasing at Clamp side, when Vin is going to lower and duty is larger.

    Well in case large input voltage range (36V to 48V), can we avoid such as voltage increasing?

    6012.200929.docx

  • 0 in reply to user5339789
    TI__Mastermind 20950 points

    Hello Takahashi,

    Mamadou made some recommendations in the driver circuit components the may help reduce voltage spikes. But I had suggested earlier to reach out specific to the LM5025CMTC controller forum since that device expert will have better suggestions on the overall power train with this power topology. It is likely that power train component changes, maybe transformer design, may be required to resolve the high voltage during power down which exceeds the driver ratings.

    Be sure in that thread to ask how to reduce the power train switching voltage during power down. And ask for advice on how to reduce this. If you just mention a broken driver they may not understand that you need to accomplish reduced voltage to resolve the issue.

    Regards,

  • 0 in reply to Richard Herring
    Intellectual 590 points

    Dear Richard,

    Yes I already started communication with controller chip engineer. And first response is to change C5 value from 0.22uF to 0.1uF.

    (which is connected between HS pin and HB pin) 

    Do you make sense to change value of this capacitor?

    regards, Keiichi Takahashi

  • 0 in reply to user5339789
    TI__Mastermind 20950 points

    Hello Keiichi,

    I looked at the MOSFET datasheet and the Qg is fairly low, so an HB to HS capacitor of 0.1uf will still be adequate to drive the MOSFET gate charge. There is some advantage in not having more HB-HS capacitance than is required since the HB-HS capacitor can charge faster during the recharge time. The controller expert may be aware of some conditions where this is important. I would try his recommendation and let them know the outcome to see if there is other advice with the power train or controller to address power down concerns.

    Regards,

  • 0 in reply to Richard Herring
    Intellectual 590 points

    201001.docx

    Dear Richard,

    Last time you can try to his recommendation in your side and will inform me that result? can you do that?

    Now we are look at this issue and tried to over 500 times with maximizing UVLO(=36V), so there is no fail even over 500 times.

    We can not see anytime to exceed abs max ratings of the gate driver. 

    Now I would like to reconfirm, do you agree to increase voltage of SW-node when power down due to PWM duty increased?

    By the way, we find another behavior that controller output unstable. Please see attached and can you give a comments?

  • 0 in reply to user5339789
    TI__Mastermind 20950 points

    Hello Keiichi,

    It is good to hear that changing the UVLO of the power DC input, I assume, has resolved the issue of switch node voltage levels that exceed the driver ratings. And you are not seeing the failures.

    Regarding the comment about can I try the suggestion and report the result, I do not have this power train hardware to do the testing for this behavior. Also the specific component values in a given application will affect the power down behavior, so even another active clamp forward design will likely behave differently.

    Regarding the scope plots, On the 1st plot I do see the narrow glitch after the initial rise, I assume this is the clamp FET Vgs voltage recorded differentially? Please confirm. Can you confirm the driver input voltage as well as the FET Vgs to see if the driver input is as you expect.

    For the second waveform, the FET Vgs of the clamp, which I assume looks like it stops switching after being stable. The switch node voltage behavior will depend on the forward FET switching and energy in the transformer magnetizing inductance and also primary current. I think once again the controller expert will have better advice.

    I can suggest from a driver standpoint. to confirm the driver input voltages and the driver output/FET Vgs to see if the driver output is following the driver input control.

    Regards,