TPS54116-Q1: Please validate my schematic design.

Hi Shintomi-san,

We will review and get back to you by 9/21.

Regards,

Weidong

Hi Shintomi-san,

The schematic looks good, although some parameters (such as compensation) might need to be adjusted based on test results. I saw you have Webench simulation results already, but test results can have some difference.

PVIN has internal UVLO function, so the part will not turn on until PVIN reaches UVLO threshold (2.7V typical). In your application, please configure the sequence so that ENSW/ENLDO rise after PVIN reaches UVLO threshold. 

Regards,

Weidong

Hi Weidong-san,

Thank you for your kind reply. Is the input method of the synchronous clock signal OK? In the case of synchronization, WEBENCH simulation rayon cannot be done, so it was carried out as a guide.

The power boot sequence is
・ 12V input is input when the system starts up.
・ Next, the FPGA that performs config and power control starts.
・ TPS54116-Q1 starts at the third timing of the FPGA, which is responsible for the main functions.
It starts in this order, so there is plenty of time for UVLO to work.

Regards,
yuichi

Hi Shintomi-san,

The synchronous circuit looks good to me. I think you can test it out when you have the hardware.

For the power sequence, I assume 12V will be converted to 3.6V first, and then 3.6V will be supplied to TPS54116-Q1, and then FPGA will send out the control signals (ENSW/ENLDO). This sequence should be ok.

Regards,

Weidong

Hi Weidong-san,

Hi Shintomi-san,

Thanks for the clarification, I don't see anything else wrong with the schematic.

Regards,

Weidong