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UCC2895-Q1: Maximum duty cycle

Part Number: UCC2895-Q1


I'm starting to test a converter using the UCC2895-Q1. I've made the necessary modifications in the hardware so I can increase the input voltage little by little seing the main waveforms and the output evolution.

Obviously, working this way, the softstart is over and the modulator is giving the maximum duty cycle (CH1 is QA, CH2 is QB, CH3 is QC, CH4 is QD and F1 is CH1 - CH3):

Is there a way to limit the maximum duty cycle working this way? I found a similar thread here, but the solution of modifying RT/CT is very limiting.

Right now I have limited the maximum duty cycle limiting the voltage on the EAP pin through a divider:

Seeing the block diagram, I expected to be possible to do it through the SYNC input, but if I understand correctly, the block diagram is not correct, as I don't see that a high-level on the SYNC pin induces a low-level on the CT and RAMP pins. I don't understand either the following description of the datasheet: "The internal SYNC circuitry is level-sensitive", as it seems it's edge triggered.

Thank you.

  • Hello Jose

    What you want to do should be possible. The Voltage Mode configuration would be a little different to the Current Mode solution so if you let me know which control method you are using I can get you some detailed advice.

    In general - in VMC you can control the duty cycle directly by controlling the voltage at EAOUT. Tie EAOUT to EAN and use the voltage at EAP to control the duty cycle.

    The same approach works for PCM but you also need to provide a current sense signal, either a CS signal from the power stage or an artificial one if you don't have a power stage attached to the controller.



  • Hello Jose

    We haven't heard from you in a while so I presume you were able to work through this issue and I am closing this thread. You may open a new - linked - thread if you wish.