• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Subscribers 64 subscribers
  • Views 368 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

UCC2897A: Vbias/VDD voltage level on PMP3162 ref design

Daniel Hintz
Prodigy 120 points
Part Number: UCC2897A
Other Parts Discussed in Thread: PMP3162, , UCC27511

For the UCC2987A reference design (PMP3162), I'm confused about the voltage level seen on the VDD pin (by way of Vbias).  The schematic shows a 36-72V input range, and the main transformer has a 2:1 (primary : auxiliary) ratio.  At a calculated Dmax=0.683, that would mean the bias output on the auxiliary winding is [(18V * Dmax) - Vd], or roughly 11.7V, not high enough to get over the 12.7V UVLO hump.  Dmin is half of Dmax, which provides the same bias voltage.

What am I missing?

Supporting doc SLUA535A (Understanding and Designing an Active Clamp Current Mode Controlled Converter Using the UCC2897A) shows calculations for a secondary side auxiliary transformer for bias generation, but I'm working on an isolated supply (bias has to be generated on primary side), so it's no help here.

Thanks!

  • 0
    Prodigy 120 points

    On a related note with the same reference design, the datasheet for the USS2897A specifies a minimum capacitance on VREF, as well as a ratio between VREF and VDD capacitance (verbiage trimmed for clarity):

    "The recommended CVREF value is 0.22μF. The minimum bypass capacitor value is 0.022μF... while the maximum is approximately 22μF. The capacitance on VREF and VDD should be in a minimum ratio of 1:10."

    If I'm reading that correctly, the capacitance on VDD should be 10x that on VREF (which makes sense given the larger current draws on VDD/PVDD)... yet the ref design has a 1uF on VREF and a 0.1uF on VDD (the exact opposite ratio).  Of course the value chosen for VREF can have a large effect on the value of capacitance required for Cboot, so it's sort of a big deal.

  • 0
    TI__Mastermind 28015 points

    Daniel,

    During start-up, VIN is connected to VDD through the UCC2897a internal JEFET and through this JFET, the UVLO turn-on threshold (12.2 V) is crossed. The IC starts switching, the internal JFET turns off and you have until UVLO OFF to bootstrap the VDD winding voltage. ~11.7 V coming from the bootstrap winding is good as long it remains above UVLO OFF (8.4 V).

    Regards,

    Steve M

  • 0 in reply to Daniel Hintz
    TI__Mastermind 28015 points

    Daniel,

    I don't believe you should draw the conclusion of a 10:1 ratio between capacitors on VREF and VDD. VREF needs a capacitor strictly for stability and 0.1uF is what I would recommend. PVDD is the bias voltage powering the driver output stage and 0.1uF might be ok when using an external gate driver. The UCC27511 should have a local VDD bypass capacitor of 0.1uF but I would also recommend a larger parallel ceramic capacitor for delivering the charge needed to drive the gates of the parallel combination of Q4 and Q6. The PMP3162 reference design seems to be relying on C21 (bias bulk capacitor) but allowing for local bulk capacitance is preferred.

    Regards,

    Steve

  • 0 in reply to Steven Mappus1
    Prodigy 120 points

    Good deal, Steve... it sounds like we're thinking along the same lines for how to support VREF/VDD.  I hadn't considered Cbulk (C21) being used after bootstrapping was done, but it IS plenty of capacitance hanging right off of the pin, so that seems logical.  I currently have a 0.1uF hanging off of VREF, a 1uF off of VDD (Cbulk comes out to around 430uF in my case), and a 0.1uF off of the gate driver, so again, we're in sync  I'll run a quick calc to see if some more bulk capacitance is needed on the driver.

    I completely forgot about the JFET on VIN... been down in the weeds too long calculating component values ;-)  Thanks!