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LM5064: Inquiry about the LM5064 reference schematic and power switch implementation

Part Number: LM5064

Inquiry about the LM5064 reference schematic and power switch implementation

1. In the LM5064 reference circuit diagram (EVALUATION BOARDS), C18 on the attached circuit diagram is open. I would like to know what the function of the capacitor is and why it should be opened.

2. To turn on the power switch, connect -48V (Low voltage) to the UVLO/EN Pin, and the PGOOD Pin fell to Low. (It is wrong on the attached circuit, but) When shut down, is there no way to keep VDD output or PGOOD high?

  • Hi Park,

    R15 and C18 acts as filter for the current shunt. This helps to provide immunity to short transient loads and avoid fast circuit breaker event. However, high value (large time constant) of filter slows down the short circuit response. For most of the systems, it may not be needed.

    Can you elaborate on question -2.

    Best Regards, Rakesh

  • Hi Park,

    Can you elaborate on question -2.

    Let us know if you have any follow-up questions.

    Best Regards, Rakesh

  • In the attached circuit diagram, the power switch is not connected to the EN pin, but I connected the switch to R6 to operate as open / -48V_IN on the EN pin to power on/off. So, when connected to -48V_IN, PGOOD becomes Low. For this reason, it is recognized that an alarm has occurred in the device connected to PGood.
    Sorry for the delay in follow-up questions due to vacation.

  • I think, it is clear. No questions from your side - right ?

    Best Regards, Rakesh

  • I tested again today. When the switch is connected between the UVLO/EN Pin and VEE, it falls below the threshold, and the PGOOD falls from High to Low, but the voltage is not turned off and the output is being made. The content of the PGOOD questioned above did not matter. I only want to turn off the output. Why not.

  • Hi Park,

    The controller disables the MOSFET when UVLO/EN Pin is connected to VEE. What is the GATE voltage and Load during this test.

    Can you share a test waveform of UVLO/EN Pin voltage, GATE voltage, load current and input voltage in a single scope shot ?

    Best Regards, Rakesh