LM5025C: Power Down sequence : reason why different behavior?

user5339789

Part Number: LM5025C

We find another behavior that controller output unstable. when power down state, Case 1 is that Clamp-SW gate(=controller output)

is keeping "High" ( green Plot ), Case 2 is going to "Low". We would like to know what happen.

Please see attached and can you give a comments?

4604.201001.docx

over 4 years ago

0 Hong Huang over 4 years ago

TI__Guru 71095 points

Hi,

Does it have any bad effect on your clamping MOSFET? Your waveforms show it occurred when UVLO_OFF, so there should not be any bad effect on you converter operation, right? Can you please clarify what is your concern?

0 user5339789 over 4 years ago in reply to Hong Huang

Intellectual 590 points

Thanks a lot for your quick reply.

Yes we have not seen yet any problems both of waveforms.

Concern is; which is better sequence to close operation more safety.

Do you think these phenomenon may be occurred when UVLO is maximum condition?

regards, Keiichi Takahashi

0 Hong Huang over 4 years ago in reply to user5339789

TI__Guru 71095 points

Hi,

There should not be difference as the operation is in UVLO-off, OUT_A stopped, OUT_B at high will become low, so it is to be same as OUT_B at low. When re-power on, both A and B will be low first.

0 user5339789 over 4 years ago in reply to Hong Huang

Intellectual 590 points

Dear

Thank you for your prompt reply.

Yes understand. We are going to double check you mentioned accordingly.

regards, Keiichi Takahashi

Power management

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LM5025C: Power Down sequence : reason why different behavior?