Thanks , I will watch
1.in the first file the boost converter example the slop compensation is use triangle waveform but in real circuit I need use the emitter follower to generate the triangle, but how do I know the RT/CT peak value in the datasheet ii just tell me the peak to peak value,if I do the slop compensation I don't need to know the peak value?
2.In the simplis I can easily to generate the triangle waveform but if I want to use like UC3842's method how do I do. Can you give me exanple about this
I run the simulation you give me
but the oscillation frequency is not like 1.72/(RT*CT) in this simulation the frequency should be like 86kHz but in the simulation the frequency is 71.89k
and the Rramp in the simulation is 5k this mean I need to try and error?
in the Simplis I can decide the value of the slop compensation like 0.36V , but if I use UC3842 How do I generate the 0.36V ? make the RT/CT waveform peak value is 1.06V and use BJT the 1.06-0.7=0.36
the method I said is correct? and in the UC3842 datasheet all I know is the peak to peak value how do I do this part I am confused
Hi
Yes, the measured frequency from the sim is ~72 kHz but from The UCC28C42 data sheet, figure 1:
The red lines drawn on the graph represent the error between the simulated value and the "ideal" value (Rt=20 k, CT=1 nF, F~80 kHz). There is ~10 kHz error between sim and calculated values. I removed the BJT from the sim to see what effect it might have on loading the RAMP signal and there was no change in frequency. The measured frequency remained exactly the same at 72 kHz but in a real circuit this can't happen - we expect some frequency shift due to minimal clock loading (base current vs removal of base current) associated with RT, CT. The sim model is close but not perfect.
Slope compensation is based on mixing/adding an amount of artificial slope to the CS signal. Slope is based on m=dy/dx but it seems you are only thinking about the peak value (dy) while ignoring the frequency component (time, dt). As you mentioned, the peak value will be reduced by ~0.7 V due to Vbe of the BJT. A single resistor from the BJT emitter to CS will add slope comp RAMP mixed with the CS signal at the CS filter capacitor. You adjust the slope comp by adjusting the peak by setting the emitter resistor and applying the superposition theorem at CS to achieve the desired amount. Think of slope comp as peak/time or peak*freq. The application note U-97 gives a clear explanation (below). Fig 2 shows the slope comp (-m) inverted (subtracted from the error voltage) but we can imagine it with +m when we add it to the CS:
Regards,
Steve M
30 mV/us is what your RAMP has available to contribute toward slope compensation. From the magnetizing inductance, you need to calculate the voltage slope appearing across the current sense resistor. The slope on the CS resistor will determine how much slope compensation is required and you know from the RAMP (RT, CT) appearing at the BJT emitter, what you can contribute. Below is an example I worked out for you. Your values may be different depending on your topology, VIN, VOUT, DMAX, component choices, etc but I hope you can follow the method. Please read the papers I referred to you, build a CMC circuit in TINA and don't worry about being exact because you can make necessary adjustments on the bench. Current sensing, magnetizing inductance (transformer design), current sense filtering, duty cycle and slope compensation - do you see how they all work together? Good luck with your design.
Regards,
Steve M
