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TPS73801-SEP: How to generate a negative voltage using TPS73801-SEP an the EN pin in a high impedance

user6324328

Prodigy 20 points

Part Number: TPS73801-SEP

Hello everyone,

I am using the TPS73801-SEP LDO in my design, to generate 20 positive voltages and i should generate the 21st one which is a negative one with the same LDO, one year ago i did see this topic in this forum, i tried to find it but in vain. Can you please tell me how to it properly?

The second question, is about the EN pin, actually I am using an FPGA to drive it, I notice that sometimes the LDO is activated when the FPGA is in a high impedance, should i understand that there is no pull down in the IC? should i put a pull down?

Regards
Hassan OU-AYACHE

over 3 years ago

0 Wade Vonbergen over 3 years ago

TI__Guru 62930 points

Hassan,

I need to research the negative LDO question and will follow up shortly.

With respect to the ENable question. Yes, you should bias this pin appropriately as there is not an internal pull up or down.

I will follow up on the first question after I check with some colleagues.

Regards,

Wade

0 Wade Vonbergen over 3 years ago in reply to Wade Vonbergen

TI__Guru 62930 points

Hassan,

I have some feedback on this.

There should be no issue doing this, as long as the LDO and source supply are floating.

The GND pin on the device needs to be the negative Vout.

Please let me know if you have any additional questions.

Otherwise if this answers your question, please click "This Resolved My Issue"
Regards,
Wade

0 user6324328 over 3 years ago in reply to Wade Vonbergen

Prodigy 20 points

That's exactly what I am looking for, thank you for your answer.

Regards,

Hassan