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TPS22919-Q1: The short-circuit protection behavior

Part Number: TPS22919-Q1
Other Parts Discussed in Thread: TPS22919,

Hi Ti teams,

I am little confused about the TPS22919's short-circuit protection behavior and mechanism. My understanding is that IC is using voltage comparator for triggering the SC protection.

The figure below is showed in datasheet:

I would like to know what detail condition of this measurement is set.

Is it using e-loader to simulate from no-load to short circuit condition?

Is the peak duration of the Iout to be the respond time of TPS22919?

Thanks for your time reading the question.

Jack Chang

  • Jack, 

    Jack Chang3 said:

    I would like to know what detail condition of this measurement is set.

    Is it using e-loader to simulate from no-load to short circuit condition?

    From the scope it looks like an programmed current load was applied to the output with a voltage limit below ground, which would cuase the VOUT<GND plateau as it tried. the other possibility is the VOUT is pulsed low by sourcemeter, below ground. both should yield the similar result. 

    To give you a 100% confident answer, let me check with my colleagues about the specific test condition of that scope capture as not to give incorrect information. 

    Jack Chang3 said:

    Is the peak duration of the Iout to be the respond time of TPS22919?

    Sort of. The timing definition is shown in Figure 29. the t_sc figure is defined as the difference in time from IOUT=ISC on the rising and falling edge of IOUT.

    This can be applied to the scope capture as well. 

    I will provide an update on the setup details once i have discussed within the team.

    please let me know if any additional questions in the meantime. 

    best

    dimitri

  • Hi Dimitri,

    Thanks for your time responding my questions.

    There is another thing I would like to ask:

    The figure below shows the recovery mechanism after SC occurred,

    But no figure shows the situation from load to SC then recovery.

    Is it indirectly suggesting that if there is loading at output then SC occurred, the recovery mechanism is not working?

    Using EVB with 1.2A at Iout then simulating SC, it does not recovery to 3.3V Vout and 1.2A Iout after SC simulation stopped.

    Can you sharing some information and reason how recovery works and its mechanism?

    Thanks for your time and kindly help on the question!

    Jack Chang

      

  • Jack, 

    I had a chat with our systems engineer, the test condition in the original figure should be using 10mOhm short test using  mosfet  as specified for the other spec tes tconditions. The -ve plateau was due to either internal ESD clamp or body diode of the FET which was used to apply the short to ground. 

    Jack Chang3 said:

    But no figure shows the situation from load to SC then recovery.

    Is it indirectly suggesting that if there is loading at output then SC occurred, the recovery mechanism is not working?

    No. If there is loading before the SC and after the SC event the short circuit mechanism will still work, and after the short is removed the device  original laod current, the Figure 25 is literally the same as figure 24 but larger timescale. 

    Jack Chang3 said:

    Can you sharing some information and reason how recovery works and its mechanism?

    Yes. Firstly, there are comparator on VIN/VOUT, across the FET, which compare VOUT-VIN against our threshold (VIN-VOUT<=VSC. Once VSC is reached, there is a 

    After short is detected, there are two ISC limits which the device can regulate to a higher and a lowe rlimit, which really depends on the nature of the short essentially. This comparison would regulate to 3A in teh event of a "softer short". So in the event this is detected, the comparator threshold is reached, the comparator switches, the internal fet driver regulates the VGS of internal fet and thus able to regulate the current. 

    For a very hard short, VOUT will be <=VSC (0.36 typ) and probably close to zero. This is the condition which is showed in fig 24/25, and the device will regulate the current down even further according to datahsset specification

    In the case of a very hard short, there is also a possibility that the device will go into a thermal shutdown as well. The device can also recovery from this shortly after, as once the device thermal shut down, the temperature will drop below the falling thrshold of 145C typ and then device will turn on again. 

    The way that the current is measured is using the Ron of the FET in lieu of a series resistor, which avoids adding unecessary series resistance and keeping the system efficiency maximized by reducing power dissipation. This is why there is a higher ranage for the regulated short circuit current "hard short" VOUT<=VSC condition, because of the phenomenon of the FET Ron varies with VGS a lot more when VGS is low, and VGS needs to be much lower than the "soft short " condition where RON is more stable.  

    Please let me know if any further questions. If this answered all your questions for now please let me know by pressing the green button. 

    Best

    Dimitri 

  • Hi Dimitri,

    Thanks for answering the question!

    I would like to ask further about the theraml shutdown behavior of 22919.

    If thermal shutdown occurred on 22919, what would be the Output waveform of Vout/Iout?

    Is it going to be current output keep cut-off or keeping high to low to high from 0 A to 0.4A?

    Do Ti team have the output waveform at the thermal shutdown scenario? 

    Jack Chang

  • Jack,

    Jack Chang3 said:

    If thermal shutdown occurred on 22919, what would be the Output waveform of Vout/Iout?

    During thermal SHutdown, device will turn-off the internal FET, there will be no current from VIN-VOUT except for unavoidable leakage. VOUT voltage will drop to 0 assuming there is still a short, of course the exact VOUT behavior depends on the output load scenario once the TPS22919 switches off. 

    So when TSD is reached, you should see a 

    Jack Chang3 said:

    Is it going to be current output keep cut-off or keeping high to low to high from 0 A to 0.4A?

    Basically the waveform: IOUT will drop immeidately , VOUT Shoudl drop quickly (depend on load), device will stay switched off until the internal temperature drops to 145C, then it will switch on again. There is potential for thermal shutdown to cycle indefinitely if the output problem which instigated the thermal shutdown is not corrected. 

    The concept is quite straightforward, though we don't have any such waveform in the d/s, i hope that the description is clear enough to give a good picture of what happens. 

    Please let me know if you have any questions. 

    best

    dimitri

  • Hi Dimitri,

    Thanks for answering the questions.

    Right now I am working on the hardware validation of TPS22919-Q1.

    I encountered some trouble with output short circuit protection validation.

    I set up the experiment with e-loader at output to draw the current load then simulating output short condition but damage not a few 22919.

    The Vin will goes low after 200us of output current reach 10A as the waveform showing below:

    Try to analyze the damage IC find out that Vin and Vout are short together on all of damaged ICs.

    It seems that the experiment I set up for validation is too harsh for 22919.

    Do you have any suggestion or relative way for me to validate the output short circuit protection of 22919?

    Thanks for your kindly help and times on this issue.

    Jack Chang

  • Jack, 

    I would recommend to try the same test as in d/s. 

    Put a reasonable load (such as by eload, sourcemeter), then short with either a mosfet or a 10mOhm nichrome or something like that. in our testing we use mosfet. 

    Best

    Dimitri

  • Hi Dimitri,

    Thanks for your advice.

    I think my validation experiment is only different from you with no MOSFET or 10mOhm to short to GND.

    Does this mean that the 22919 directly short to GND withouot 10mOhm or MOSFET leading to high chance of IC damage?

    Another point to double confirm with you is that if I want to use the same way as you mentioned, I need to connected N-MOS's drain to 22919's output, source to GND and additional EN signal to gate. Using EN signal goes High to short and duration of EN signal High is about hundreds micro second. Do I get your point correctly?

    Jack Chang

  • Does this mean that the 22919 directly short to GND withouot 10mOhm or MOSFET leading to high chance of IC damage?

    no. 10mOhm is basically the RON of the mosfet. you can short to ground, the device can sustain this type of short over and over. It may be something to do with the current eload, by forcing too much current, it can try to pull vout far below ground, this can cause damage, fortunately this doesn't represent real life case. 

    Jack Chang3 said:

    Another point to double confirm with you is that if I want to use the same way as you mentioned, I need to connected N-MOS's drain to 22919's output, source to GND and additional EN signal to gate. Using EN signal goes High to short and duration of EN signal High is about hundreds micro second. Do I get your point correctly?

    Yes, this is correct. 

    Best

    dimitri