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Original question:

TPS53626: Operation in inaccurate pin-strapping setting

TPS53626: Purpose of the OCP setting

MINKYUNG KIM
Expert 1250 points
Part Number: TPS53626

Hi team,

I wonder the purpose of ICCMAX setting and OCP setting. As per the related thread, "The SVID bus has an alert triggering when Iout reaches ICCMAX (under normal operation it should not reach higher than ICCMAX), and we have seen instances before when the ICCMAX alert caused CPU to fail to boot up or created a hangup (or hardware check) situation".

Let's suppose that I_ccmax of the rail is 50A and OCP level is set as 50*1.3 = 65A. SVID bus will trigger the alert signal when the output current reaches at 50A and the alert signal may cause CPU to fail to boot up. From my understanding, these alert signal and boot-up failure happen when OCP is triggered. If they happen with ICCMAX setting in this case, what is the reason of OCP level setting? 


Thank you.

  • 0
    TI__Genius 11095 points

    Hello, 

    You can think of ICCMAX as a warning to the CPU that the current is higher than expected. It is only incidental that ICCMAX warning sometimes causes the system to hang up. The TPS53626 does not take any action to protect the power supply when an ICCMAX event triggers, only setting the Alert# and Status1 bits in SVID. ICCMAX is a required register/behavior from Intel. 

    OCP is meant to protect the VR from overload events. TPS53626 will not fire pulses to any phase whose current measures greater than the OCP threshold. It is meant to prevent inductor saturation and power stage/FET damage due to overstress. 

     

  • 0 in reply to Matt Schurmann
    Expert 1250 points

    Hello Matt,

    Thanks, I understand the difference between them. Then could you advise the general setting value of OCP in relative to ICCMAX? Is it generally okay if I set it as 1.3*ICCMAX?

  • 0 in reply to MINKYUNG KIM
    TI__Genius 11095 points

    It depends on the tolerance of your DCR and temperature compensation. 30-50% is typically an adequate amount of margin.