UC3842: Synchronization

Hi there! 

Thanks for reaching out and for your interest in the UC3842! The synchronization function of the device allows the user to bypass the IC's oscillator by providing an external oscillating signal. As the datasheet states, this external signal (be it from an FPGA or a microcontroller) can be applied between the low side of the timing capacitor CT and the high side of a small resistor placed between CT and ground. This feature is useful for systems using multiple PWM controllers commanded by a master device and can ensure a more accurate duty cycle and reduce output ripple. 

Thank you for getting in touch, I hope this information helps! 

Aidan Davidson

1. Yes, the PWM output is turned on when the capacitor begins charging but the PWM output doesn't turn off when the capacitor begins discharging, it turns off when the amplitude of the voltage on CT meets the value set by your circuit conditions. When your output turns off (your duty cycle) is determined by the feedback the PWM controller is receiving from the power stage. When your output voltage is low, your threshold for PWM output turning off (and your duty cycle) is higher. When your output voltage is high, your threshold for PWM output turning off (and your duty cycle) is lower. This means that there is a separate threshold above that where the capacitor begins discharging. Check out the image below: 

From this figure, your PWM output would actually turn off when the voltage on CT reached the "error amplifier output" line. CT will continue charging until it reaches the upper comparator threshold. The addition of the synchronization pulse forces the voltage on CT to hit that upper threshold before CT is charged up to that value and triggers CT to immediately begin discharging. 

2. You won't be making sure that the synchronization pulse is perfectly matched at the peak of the RT/CT waveform. The key here is to choose the amplitude of your synchronization pulse such that no matter where in the CT charge/discharge cycle the pulse arrives, CT is immediately triggered to discharge and restart the PWM output cycle. 

1. The synchronization pulse forces a reset of CT voltage. If the CT voltage is below the error amplifier threshold when this happens, the PWM output will turn off. If the CT voltage is above the error amplifier threshold, the dead-time will be shortened before the PWM output turns on again. You can definitely tune the switching frequency using the synchronization signal within the constraints defined in the datasheet (osc. frequency should be ~20% of sync. frequency). 

2. The synchronization pulse has a lot of different benefits, the two biggest are the ability to synchronize different PWM controllers in interleaved power systems and the noise benefits, take a look below for a relevant figure: 

Noise on the CT ramp can cause premature triggering of the device oscillator, the addition of the sync pulse can help prevent this. Other benefits are captured below: 

See pictured below 1 capacitor cycle and how it controls the PWM output. If the sync pulse occurs before line 1, the PWM output will prematurely turn off, essentially the sync pulse will skip forward in the cycle to after line 2. If the sync pulse occurs between line 1 and 2, the PWM output will already be turned off, but the capacitor will begin discharging immediately (skip forward in the cycle to after line 2). After line 3, the cycle restarts, the PWM output turns on and the capacitor begins charging again. 

You can't decide the pulse position without inhuman reflexes. The PWM output will be affected for only a moment as the sync pulses begin arriving, not enough to cause any system issues. 

Hi again, 

Tuning the oscillator frequency with a sync pulse will, by definition, affect the timing of the turn off and turn on of your PWM output. If you do not want to affect this timing, a sync pulse is not the way to go.