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TPS54386EVM: DC bias for MLCC cap

Part Number: TPS54386EVM

Customer would like to do the simulation for the loop gain/bode plot with real selected components. As we know, the capacitance losses with ceramic need to be considered with DC bias voltage. On the TPS54386EVM, we see there is an application curve of the loop gain response. Is DC bias voltage for MLCC being considered? Or it didn't consider it?

We're confused if we need to take the capacitance loss into account in real calculation for loop gain response performance? Please help on it.  


Brian W

  • Hi, Brian 

    1. Yes, the bode plot considers the capacitance degrading at DC bias voltage. 

    2. Yes, we must take the capacitance loss into account for loop response. 

  • Thanks.

    We don't think that the DC bias voltage derating was not taking consideration for capacitance losses on this TPS54386EVM, right? How come?

    For the compensation, the calculated freq. is 6.79Khz according to the Bom's L&C components. (In the d/s, it needs to be in the range of the 6Khz to 7KHz for optimized compensation). So DC bias derating for MLCC components should NOT be taken into account on this EVM.

    We're confusing on this, please help on this. very thanks.  

  • Hi, Brian 

    Considering the capacitance loss, I think the EVM design is not a good one.  

    I believe we must take the capacitance loss into account for all of designs. 

    Thanks for pointing this out.