UCC27511: UCC27511 IC OUTH and OUTL with different voltage level

Hello,

Thank you for reaching out.

I have review the waveforms and I have several comments and clarifications based on the details you provided.

1. Are the measurements consistent across several IC's? across several boards? Have we done ABA testing? Can you please confirm the component values around the gate drive portion? 

2. Can you also share if possible the input signal on pin 6 on the driver? I ask to make sure the input signal is fully crossing the input thresholds VIH and VIL. 

3. It seems the Vgs voltage saturates around the Miller region on the first waveform while on the next cycles, the gate voltage appears to get stuck around the same region before eventually saturating to the full gate drive voltage. The waveforms appears to rule out the VDD supply which is stable throughout the cycles which brings me to the load and what type of FETs is the output stage driving? (MOSFET PN, gate charge, Qg, etc...) I ask to confirm that the load is adequate for the drive strength capability of the IC specifically at the miller region.

4. On the last waveform, the duty cycle seems to significantly decrease in addition to the gate voltage drop. I presume operation is at constant duty cycle, please confirm. Can you also please share zoomed in waveforms on one of the cycles (when the voltage get stuck)? 

Regards,

-Mamadou

Hi Mamadou,

Thanks for your quick reply and comment, please see below for detailed information and we can discuss again.

Basically, this symptom only can duplicate in our factory but no in our LAB, even we use the same unit from the factory still cannot duplicate the issue.

Q1: 

1. Are the measurements consistent across several IC's? across several boards? Have we done ABA testing? Can you please confirm the component values around the gate drive portion? 

The symptom can be duplicate in our factory field side on each board, I'm not sure about your ABA testing and component values? Do you mean the gate drive voltage?

Q2:

Can you also share if possible the input signal on pin 6 on the driver? I ask to make sure the input signal is fully crossing the input thresholds VIH and VIL. 

Please refer to the file as attach which has a pin6 signal during abnormal.0363.UCC27511 waveform.docx

Q3:

It seems the Vgs voltage saturates around the Miller region on the first waveform while on the next cycles, the gate voltage appears to get stuck around the same region before eventually saturating to the full gate drive voltage. The waveforms appears to rule out the VDD supply which is stable throughout the cycles which brings me to the load and what type of FETs is the output stage driving? (MOSFET PN, gate charge, Qg, etc...) I ask to confirm that the load is adequate for the drive strength capability of the IC specifically at the miller region.

The MOSFET PN is IPZA60R045P7

Q4:

On the last waveform, the duty cycle seems to significantly decrease in addition to the gate voltage drop. I presume operation is at constant duty cycle, please confirm. Can you also please share zoomed in waveforms on one of the cycles (when the voltage get stuck)? 

Please refer to the file as attach which has a pin6 signal during abnormal.

Hello, 

Thanks for the details.

It seems the IC is driving a 4-terminal FET with a kelvin pin connection, can you please verify connections of Source terminal and kelvin pin?

Additionally, are there any sense resistors at source (GND) of the MOSFETs? I ask because in some case, you may have voltage building up across the sense resistor and creating a voltage drop across the IC GND reference that might cause trip up the input signal and/or output signal which are supposed to referenced to 0V. Can you confirm?  

From the last waveform you shared, the issue seems to revolve around the input signal which is not saturating to the expected 6V where during the 2nd pulse there is significant chatter causing the input signal to oscillate above and below the input threshold. Can you please verify your input filter size  C113 and the corresponding Rin on pin 6?

May you also share the rest of the component values? 

I meant by ABA testing, if you remove the IC from board 1 and place it on board 2, does the issue follow the IC at factory side?  

Regards,

-Mamadou

Hi Mamadou,

Yes, the MOSFET is a kelvin source configuration, and the waveform I provide VGS is kelvin S and the VDS source is connected to power GND.

Additionally, are there any sense resistors at source (GND) of the MOSFETs? I ask because in some case, you may have voltage building up across the sense resistor and creating a voltage drop across the IC GND reference that might cause trip up the input signal and/or output signal which are supposed to referenced to 0V. Can you confirm?  

Actually, we do have a current sense resistor and that is for PFC current loop control, also I can duplicate the issue now.

During abnormal waveform, It can observe UCC27511 pin 5 have noise at the same time, Increase C113 can improve this situation?  and how much capacitance you recommended? 

CH1/CH2 is VGS/VDS of PFC 

CH3 is UCC27511 pin5 for your reference.

I meant by ABA testing, if you remove the IC from board 1 and place it on board 2, does the issue follow the IC at the factory side?  

From now, we can observe this situation in each unit. so there is no ABA that can swap the ICs.

Hello, 

That's great that you're able to reproduce the issue in your lab.

Unfortunately the picture you want to share did not attach correctly for review.

I would recommend increasing C113 but I do not know what any of the component values are.

Additionally, it may be important to know where the noise is coming whether it is PCB layout related, GND issues, etc...

Regards,

-Mamadou 

UCC27511 IN- noise.docxHi Mamadou,

Attach waveform for review.

About C113 capacitance value is 10pF, increase the capacitance will affect driver ability or not?

About the layout  GND issue, you can also check attch thatl IN- waveform with sine wave and follow input current. 

Hello,

Thanks for the additional information.

From the waveforms there appears to be some GND ground likely due to high dVgs/dt and/or high di/dt from the PFC stage. The GND bounce seems to be consistent with the rising/falling edges of the Vds voltage. I suspect the ground return loop to the input stage is quite long in which case you the consequent di/dt through the MOSFET and parasitic inductance on the GND traces will induce the voltage you're seeing on CH-4 from V=Lss*di/dt.

There are several mitigating actions we can take including (i) slowing down the dv/dt at the gate with higher gate resistance to consequently slow the MOSFET di/dt. This is will obviously impact your overall efficiency by because of the switching losses on the FET. (ii) The second mitigating action is increase the input capacitance (as you rightfully suggested) which is currently too small to adequately filter out the transients on the input stage. Increasing the cap will not impact the driver performance so long as Rin <=100-Ohms AND C113<=200pF. (iii) The third mitigating item I suggest to try is adding a clamp diode on the input pin to help maintain IN_GND voltage within range and prevent false triggering and/or oscillations.

Please let us know if you have additional questions.

Regards,

-Mamadou    

Hi Mamadou,

Thanks your quickly response and suggestion.

 Plan (i) may not be an option becouse of efficiency impact and thermal concern.

Plan (ii) I can quickly check and see the result, by the way what the Rin you mentioned?  it's MOSFET or you mean PFC gate resistor?

Plan (iii) i also can try. let me confirm the connection, do you mean Clamp diode Cathode connect to IN- and Anode connect to IC GND, right?  

Hello,

For plan (ii) I meant Rin series resistance with C113 to filter input signal (pin 6) to mitigate GND bounce.

Plan (iii) I meant clamp diode from IN+ (pin 6) to GND which will be parallel to C113.

Regards,

-Mamadou

Hi Mamadou,

Plan (iii) put a clamp diode from IN+ (pin 6) to GND which will be parallel to C113 but the noise is come from GND to IN- (pin 5).

It can help that symptom and avoid noise coupling from GND?

Hello,

We may try plan (iii) if to plan (ii) show limited results to limit GND bounce influence on input signal and protect the driver. As you know, the driver input pins will not tolerate excessive long duration negative pulses. The clamp diode will help maintain a steady voltage on IN+ which might help limit risks of false turn-on during GND shift.

Regards,

-Mamadou

Hi Mamadou,

I have try that plan (iii) but still can capture pin 6 with negative votge during start-up and this waveform may affect MOSFET VGS full turn on.

please see attach file.

Plan (ii) did not help even increase the capacitance further.

7266.UCC27511 IN- noise.docx

Maybe we can discuss by phone call or skype, may i know the time when you available?