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# LM5160A: LM5160A buck circuit stability problem

Part Number: LM5160A
Other Parts Discussed in Thread: LM5160DNTBK-CALC, LM5160

HI

below is the SCH for the buck circuit design using LM5160A, input voltage is from 40V to 60V, the problem is: the inductor temperature is very high even when the load is small or none.

the SW waveform is as below when there is no load added:

it's the stability problem.

I use TYPE3 ripple configuration.

The parameters of RON(R4=681k) , RA(R1=402k), CA(C1=3nF), CB(C6=10nF) are from Webench power designer, also i calculate these values based on application note AN-1481. No problem was founded.

can anyone help to look at this? any feedback is welcome.

Thanks

• Hello

Please use the attached calculator tool to double check you component values.

Thanks

• Please see attached file for the layer. thanks

PWB layer.docx

• sorry, I didn't see the attached calculator?

• Jian,

You can find the LM5160DNTBK-CALC calculator here.

For type-3 ripple network stability we have suggested 20mV ripple amplitude, which usually works for most low-voltage outputs.

I think your 24V output has larger output ripple, that dominates type-3 ripple and will lead to instability.

Try reducing RA to ~300kΩ to increase type-3 ripple and stability should improve.

Hope this helps,

-Orlando

• Hi

After going through snva874, there are some calculations which is not same to application AN-1481.

1: CA:   in snva874, CA>=10/[FSW*(RFB1//RFB2). but in AN-1481, CA=10/[2*pi()*FSW*(RFB1//RFB2),

2: CB: the calculation is not same, in AN1481, CB is 3 to 4 times larger than CA.

my test shows decreasing RA to 200K, CA to 1nF will be better than before, but the SW waveform still have some fluctuation like below that makes the ripple voltage fluctuating.

when using signal trigger mode

For the calculation tool, this is for LM5160 which maximum current is 1.5A which CA is 1nF and RA is 51.1K, CB is 0.1uF. in this configuration, there is a little improvement, the fluctuation is still exists.

Do you have any recommendation or keeping reducing RA value?

BTW, does the layout have any problem? thanks again!

Best regards

• Any suggestion? thanks

• Jian,

I dont think you should change CA, I would keep it at 3.3nF.

What does it look like with 3.3nF & 200kΩ?

Can you share your copy of the quickstart tool?

On your layout, the footprint for VCC cap is very big, and your FB node routing is much longer and far from the IC.

See section 10.2 of the datasheet. I would reduce the footprint of the C12 cap and improve the FB node routing, also avoid the 90 degree angle.

This node is critical for stability so I think it is could be causing your jitter issue.

-Orlando

• Hi Orlando

the waveform will be uploaded later.

Attached is the calculation for the RA/CA/CB. you are right, FB length is a little longer, will be adjusted as below:

BTW, any recommendation for the replace of the LM5160A for low power dissipation, I am afraid the chip's temperature will be very high if running with 24V@2A load even the SW jitter problem is fixed.

thanks again!

LM5160A Cal.xlsx

• when RA=200K, CA=3.3nF, CB=0.01uF, the SW waveform is as below:

using single trigger:

it is still unstable.

thanks

• Jian,

Looks like your best results were with the 200kΩ and 1nF.

How hot is your IC? Maybe you can add more thermal GND vias around the IC. Also thicker copper will help with temperature.

See section 6 in: https://www.ti.com/lit/an/snva183b/snva183b.pdf

Also swap the placement of C10 and C7. The ceramic capacitor handles the high-frequency switching current and should be closest to VIN and the GND pin of the IC to reduce the parasitic inductance. Right now the C10 GND has a big top layer loop.

-Orlando