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Original question:

BQ76930: bq76930 equalization FETs damaged during short circuit tests

CSD17484F4: VGS max specification whether it applies to Maximum VGD voltage possible in Circuit

first_name Koppanati
Prodigy 230 points
Part Number: CSD17484F4

Hi,

We are planning to use CSD17484 MOSFET in our design.

it will be used at multiple places, 

In one of the circuit, Drain can go up to 15V peak (rarely, typical always stays @ 13.2V), Source is GND, Gate will be driven either 0V or 3.3V.

In this case, sometimes we see VGD is up to -15V (worst case for short time).

I didn't VGSS spec in the datasheet (VGSS - Max VGS with Drain and Source are shorted), 

Is the Max Voltage VGD = -15V will problem for this MOSFET (Can i use VGS max specification to compare VGD worst case voltage).

  • 0
    TI__Mastermind 29525 points

    Hi,

    Thanks for your interest in TI FETs. You should have no problem operating the FET as described: VDS = 15V & VGS = 0V (i.e. VGD = -15V).

  • 0 in reply to John Wallace1
    Prodigy 230 points

    Thanks John,

    One doubt remains,

    To verify

    Whether MOSFET with stands Circuit's Maximum VGS - VGSS/VGSmax specification is available

    For Max VDS in the circuit - VDSS/VDSmax specification available,

    Is there any specification in the MOSFET datasheets which can give information on Max VGD a MOSFET can withstand or can we deduct something from VGSmax & VDSmax specifications like VGSmax-VDSmax to get VGDmax.

    I am under the impression that VGS max is the specification for Gateoxide layer breakdown, which is common between whether it is Gate to Source or Gate to Drain - am i correct?

  • 0 in reply to first_name Koppanati
    TI__Mastermind 29525 points

    Hello,

    I've consulted with my colleagues. You're correct that the max Vgs rating is to prevent breakdown of the gate oxide. Basically, when the gate to source is biased, some current is tunneled through the the oxide. However, even at the max Vgs, the amount of charge injected by this current is still much less that the Qbd (breakdown charge) such that the long term reliability of the gate is not in any danger.

    But when the Vgs exceeds the max rated value, the tunneled current increases exponentially and the robustness of the gate can no longer be guaranteed.

    The internal geometry of the gate's position with respect to both the drain and source dictate that the most stress will be absorbed from gate to source, not gate to drain. In other words, the max Vgd is not the same as the max Vgs, and is much greater such that the max Vgs or max Vds will always be exceeded first.

    TI does not specify or test VGSS. There is no risk or problems operating the FET with VDS = 15V and VGS  = 0V.

  • 0 in reply to John Wallace1
    Prodigy 230 points

    Thanks John,

    That clears my doubt,

    I am looking any approximate quantitative assessment of VGDmax from datasheet parameters like may ne 80/120/150% of max(VGS,VDS).

    I expected it <VDmax because Gate to Source clearance is 0.2mm, Drain to Gate clearance is 0.4mm in package (crude approximation is VGDmax = ~2*VGSmax).

  • 0 in reply to first_name Koppanati
    TI__Mastermind 29525 points

    Hello,

    I'm afraid I do not have any additional information or data to share regarding VGDmax. Perhaps I can provide better support if you can share more details about the application. If not, then I am going to close this thread.

  • 0 in reply to John Wallace1
    Prodigy 230 points

    Thanks John, I got enough information to proceed. I stretched your time - thanks again.

    I can't share the application information over open forum.