LM25066: Connecting Pull up to external 3.3V other than VDD

praveenkumar vh

Part Number: LM25066

Hi,

Im using LM25066 for hotswap application, where i want to put RETRY# into latch off mode.

so i have made RETRY# to pull up with external 3.3V supply, is it ok to connect or we need to connect to VDD only which is coming out from LM25066.

i need same clarification on all strap and control signals.

1. RETRY, CB, CL, Power GOOD, SMBA, Address line and DATA/CLK lines.

Found issue after connecting RETRY# to external 3.3V, FET is showing dead short.

thank you,

Praveenkumar

over 4 years ago

0 praveenkumar vh over 4 years ago

Prodigy 130 points

Schematic is attached.LM25066 schematic ATOS.pdf

0 Praveen GD over 4 years ago

TI__Guru 57737 points

Hi Praveen,

RETRY/, CB, CL pins can be pulled up to external 3.3V. The Input High threshold for RETRY/, CB and CL pins is 3V as shown below.

Similarly, Power GOOD, SMBA, Address line and DATA/CLK lines can also be pulled up to an external voltage as long as the external voltage is within recommended operating conditions mentioned in the datasheet.

External pull up of RETRY/ has nothing to do with FET failure.

Can you share the filled in design calculator of review. The design calculator is available in the LM25066 product folder in TI.com.

Please go through the videos in below link before using Design Calculator.

https://training.ti.com/node/1133677

https://training.ti.com/node/1133673

https://training.ti.com/node/1133664

https://training.ti.com/node/1133681

0 praveenkumar vh over 4 years ago in reply to Praveen GD

Prodigy 130 points

Hi praveen,

Thank you for confirming of using external supply to any strap signals of LM25066 within the recommended voltage range.

Now FET failure happened in my case during the dead short testing and RETRY# was given to external 3.3V.

i have attached the design filled design calculator and schematic4428.LM25066 schematic ATOS.pdf New LM25066_Design_Calculator_REV_D.xlsx for review.

Please help me to find root cause of FET failure.

And there is diode i connected between FET out put to GATE (normal switching diode as suggested in design calculator), will it causes any problem ?

thank you

Praveenkumar

0 Praveen GD over 4 years ago in reply to praveenkumar vh

TI__Guru 57737 points

Hi Praveen,

In the design calculator that you have shared cell No. F62 has been tampered because of which the the 'Maximum steady state FET Junction Temperature (TJ,DC)' , 'SOA margin during "hot-short" or "start-into short"' calculations have gone wrong.

You are not supposed to edit the cells in White.

Your design doesn't have enough SOA margin during "hot-short" conditions. You need to use at least 2 FETs for the design to make it robust. Please see attached correct design calculator below. Few changes have been made to the FET SOA parameters. To understand more on how these changes were made, please refer to the training videos that I have shared earlier. New_LM25066_Design_Calculator_REV_D.XLSX

Also in the schematic, I don't see a TVS at the input of the Hotswap. Please use a SMDJ12A TVS close to the VIN pin of the controller. To understand more about the importance of TVS in hotswap circuits and its selection please refer to the below attached document.

7725.TVS Clamping in Hot-Swap Circuits.pdf

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LM25066: Connecting Pull up to external 3.3V other than VDD