TPS62366A: The reason why switching frequency changes with PWM mode

Hello user,

TPS62366A is based on DCS control topology, please have a look at the following App Note discussing about frequency variation in the DCS control topology.

Let me know if you have any questions!

Thanks,

Dorian

Thank you for an answer.
I am sorry, but have not been able to yet understand the contents of the document which had you provide it.
It seems to take time a little more.

Hello user,

If you have any questions about the content please ask.

We are always welcoming feedback.

Thank you!

Regards,
Dorian

Thank you for an answer.

Please tell me the reason why On_time of 2.5MHz of figure 2 (b) grows big in 8V or less.

It means that Off_time shortens to make up for a loss, will it can be calculated switching frequency if a loss can calculate?

Hello user,

The TPS62130 was shaped for up to 17V down to 3V input voltage operation. This means that the power stage was also built in a way that it can sustain low input Voltage operation. What you see with this higher on_time of figure 2b is the system trying to compensate the higher Rds_on 90 to 120 for High side MOSFET and 40 to 50 for Low side MOSFET) that the step-down converter will have at lower input voltage.

The system is not calculating losses but just adapting its switching frequency depending on VIN voltage. 

TPS62366 was shaped for 2.8V to 5.5V input voltage and do not have this limitation. 

What you are seeing only applies to DCS control with wide VIN operation like TPS62130.

Let me know if you have any other questions!

Thanks,

Dorian 

According to the documents you provided, the switching frequency tends to be lower than the nominal value.
It was understood that the switching frequency decreases because the time of Ton is extended by the delay time of the gate drive in the IC, and as a result, the Toff is also extended.
Is this delay time fixed for each IC?
Is it possible for you to tell me the delay time of each IC from TI?

Hi User,

Dorian is out for a few days, but let me comment until he returns.

The reason for the small increase in frequency from 1A to 4A is as it is explained in the app note:

In Figure 2a, the frequency increases with heavier loads due to losses. Higher loads require slightly higher duty cycles to overcome resistive losses in the circuit. Since the on-times are the same for both the 1-A load and 3-A load, the off-time is decreased to achieve the higher duty cycle (Figure 2c). The same on-time and a shorter off-time results in a shorter period and higher frequency.

It looks like you are looking for a device for a specific application.  Can you share any details of what you need: Vin, Vout, Iout, features, etc.?

We have our new TPS62864/6/8/9 family, which is newer, smaller, better than the older TPS62366A and TLV62095.

The mechanism by which the gate drive delay increases the switching cycle is shown in the diagram. Is this correct?

And again, is the delay time described here fixed for each IC?
If so, would it be possible for you to let me know the delay time for each IC from your company in response to my request?

Thank you.

TPS 62363 data sheet.

www.ti.com/.../tps62363.pdf

Page 24 of the datasheet says 20 ns.
Is this the delay time of the gate drive?

Hello user,

Indeed, a small delay time extends the on time. This value is not strictly specified nor tested in production.

You can take 20 ns for calculation here.

How does it affect your application?

Let me know.

Thank you,
Dorian 

Hello.
We are not concerned with switching cycle changes, and we do not want to suppress them.
We want to calculate ripple noise without simulation or measurement.
The reason is that you want to calculate ripple noise quickly without simulation or measurement.
As you know, the waveform of the coil current that causes ripple noise is affected by the ON time, OFF time, switching period, input voltage, output voltage, and inductor value.
And we found that the switching cycle changes.
Therefore, we thought it would be possible for your company to inform us of the switching cycle depending on the type of IC, input/output conditions, load conditions, and circuit conditions.

Hello user,

As previously mentioned, this 20ns is the value you should use for your calculation.

Let me know.

Thanks,
Dorian  

Thank you for your reply.

Looking at the composition of the expression, 20 ns seems to be the delay time.
But is 20 ns not a physically meaningful value representing the delay time, but just a constant in an approximation?

Also, the switching frequency cannot be accurately determined by the formula in the data sheet.

If the delay time cannot be strictly defined or disclosed, does it mean that there is no choice but to obtain it each time by measurement or simulation?
At the very least, it would be helpful if there is an indication that the delay time is between A and B.