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TPS62175: SLEEP mode drawing more current than non-SLEEP mode?

Part Number: TPS62175

We are working to minimize power consumption in our battery-powered product.  We observed the unexpected behavior that the TPS62175 is consuming slightly more current in SLEEP mode than in normal mode.  We'd like to verify that we're using the part properly, or at least have a good explanation for this behavior.

The basic setup: 

  • input voltage nominal 7.2V
  • output voltage 3.3V
  • Feedback divider network: 470K / 150K (5.3 uA flowing through the divider)
  • Approximately 350 uA load on the output

According to the data sheet, with a load of 350 uA, the part is predicted to have an efficiency of ~75% in SLEEP mode and draw about 4.5 uA quiescent current, compared to ~70% efficiency and 22 uA quiescent current.

But on the input side, we're seeing a load of ~163 uA in SLEEP mode but only ~158 uA in normal mode.  

Why is the current consumption higher in SLEEP mode than in normal mode?

  • Robert,

    As the quiescent current specification in the datasheet is taken without the device switching, one has to be careful comparing the running input currents between these modes, and you cannot simply assume that you will see a ~17uA delta between the two operating modes as the device current only falls to 4.8uA (typ) when neither the high or low side FETs are active (ie during discontinuous conduction).

    BTW, If I calculate the efficiencies by simply using your input and output voltages and currents (Vo*Io)/(Vin*Iin), I see that you are getting nearly 100% efficiency, which likely means that there is possibly an issue with the measurement(s).

    Could you please provide the SW pin switching frequency and output voltage ripple waveforms for sleep mode and normal mode?

    Additionally, what are the inductor and output capacitor values that are you using?

    This will determine how much peak inductor ripple current and output voltage ripple is generated on each PWM pulse, and if you are not seeing extended periods of discontinuous conduction in sleep mode, you will not get the maximum power savings.

    Sincerely,

    -Matt

  • Hi Matt:

    Thanks for the prompt reply. 

    > Could you please provide the SW pin switching frequency and output voltage ripple waveforms for sleep mode and normal mode?

    I haven't measured the SW pin switching frequency because -- if my memory serves -- the frequency isn't constant when there's a very low load (as is the case here).  If I'm wrong and you want me to fire up the 'scope, I'd be happy to oblige.

    >  What are the inductor and output capacitor values that are you using?

    The inductor is 10 uH and the effective capaciitance is "huge": in addition to 22 uF and 1.36 nF high-frequency capacitors, there is a 1.5 F supercap hanging on the 3.3V rail.  

    >  I see that you are getting nearly 100% efficiency, which likely means that there is possibly an issue with the measurement(s).

    Guilty as charged!  I can only measure the current going into the system, so I back-calculated the output current assuming constant power on input and output.

    I'm still working on minimizing the load current -- once that settles down, I'll take some fresh 'scope readings to see how the switcher is performing in both modes.  But let me know if there's any issue with hanging a large capacitive load on the output.

    Thanks in advance.

  • Robert,

    You are correct that the swicthing frequency will vary some under light load conditions, but provided the load isn't dynamically changing and the ripple on the output voltage is fairly stable you should see a reasonably stable switching frequencies.  Alternatively, as its primarily the discharge time that varies in these conditions, you should be able to at least capture a stable on-time pulse on the SW, and it would be good to confirm if you are getting the expected 2x Ton in Sleep mode vs PSM.  Additionally, if the SW waveforms are not easily captured, a good AC coupled (or DC zoomed) trace of the output ripple voltage should also provide a good view of whats going on in the regulator stage.

    However, I a bit concerned that the supercap may impacting your measurements and performance as you do not want our device trying to regulate the supercap's output voltage instead of the 22uF cap.   If this is the case, I suspect you are be getting periods of "bursting" out of the regulator as we pump up the output voltage followed by long periods of idle operation as the voltage discharges.  In practice, this may not be a problem for your application, but depending on when you take your current measurements and how long it takes the supercap to discharge between "bursts", you are going to see periods of higher switching currents followed by long periods of low idle currents.

    Is there any type of separation/filtering between the 22uF and 1.5F supercap?

    Would you be able to remove the supercap and measure the performance with just the 22uF output cap?

    Thank you,

    -Matt