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Thanks for your interest in TI FETs. The transient thermal impedance curves are based on power dissipation and not current. The temperature variation of on resistance is not really relevant to the curves in the datasheet. Your power dissipation calculation should take into account the temperature variation of on resistance. Multiply the I2R loss by the normalized on resistance shown in Figure 8 of the datasheet at the operating temperature of the FET. For example, at 100degC & VGS = 4.5V, the normalizing factor is about 1.4. That should give you a better estimate of the power loss.
thank you anyway for the answer! But I didn't say that the transient thermal impedance curves are based on current!
It is still not clear to me, therefore I will repeat my calculation and I will ask again my questions:
Apologies for any confusion. You are correct that the power dissipation is going to increase because on resistance goes up as the device self heats. My approach was to assume that the on resistance was at its maximum due to temperature rise during the entire pulse. This is worst case and may over estimate the junction temperature rise. Another approach could be to average the loss at the beginning, where the FET is cooler, to the end of the pulse when the junction temperature is higher. For example, use (1.176W + 1.53W)/2 for your calculation.This assumes a linear increase in rds(on). I just want to make sure you're not underestimating the temperature rise.