• State Resolved
  • Locked Locked
  • Replies 16 replies
  • Answers 7 answers
  • Subscribers 62 subscribers
  • Views 650 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

LM5025C: Broken Issue : Active Clump with UCC27200

LM5025C: Idea to use precision voltage detector and latch to control surge and timing

user5339789
Intellectual 590 points
Part Number: LM5025C
Other Parts Discussed in Thread: LM5025, TPS37100

Dear

I posted today a related question but I couldn't see the history of today's post, so I'd like to resend it

We still worry about behavior of PWM controller and the gate driver.

When activated and power down,  passing through a transient input voltage A short-time and high-voltage surge occurs on both the primary and secondary sides Too much times gate driver has been broken and we do fine tuning to adjust components values.

Well our engineer is try to Use high-precision UVLO and timing control to prevent surge.

Could you give your comment how you think this idea?  Attached is simple block of the active clump.

ACF-PS_desc-P3.pdf

regards, Keiichi 

  • 0
    TI__Guru 74115 points

    Hi,

    What is your secondary SR MOSFET drive circuit? Is it self-driven, or control driven?

  • 0 in reply to Hong Huang
    Intellectual 590 points

    Dear

    Our engineer mentioned this is control driven.

    And we are using TPH1500CNH as SR MOSFET.

    I will make a new post to describe this unexpected behavior.

    Thanks 

  • 0 in reply to user5339789
    Intellectual 590 points

    Earlier I posted that UVLO might not be working properly. So we have been looking at external circuits that complement that functionality. This time, I posted it so that you can judge whether they are out of date or not. See the attached drawing. The problem is that it restarts even though UVLO has stopped, but it is an attempt to latch the Low state and suppress the restart with more accurate voltage detection. Would you please agree with this attempt?

    ACF-PS_desc-P62.pdf

  • 0 in reply to user5339789
    TI__Guru 74115 points

    Hi,

    If you pull down SS low and keep UVLO < threshold, there should not be PWM pulses.

  • 0 in reply to Hong Huang
    Intellectual 590 points

    Previously posted that UVLO might not be working properly. So we have been looking at external circuits that complement that functionality. This time, I posted it so that you can judge whether they are out of date or not. See the attached drawing. The problem is that it restarts even though UVLO has stopped, but it is an attempt to latch the Low state and suppress the restart with more accurate voltage detection. Would you please agree with this attempt?

    0005.ACF-PS_desc-P62.pdf

  • 0 in reply to user5339789
    TI__Guru 74115 points

    Hi, 

    Again, if Line UVLO < threshold, there should not be pulses, if you see pulses, when UVLO < threshold, please capture the waveform of UVLO, OUT_A and OUT_B, to show at UVLO < threshold, OUT_A and OUT_B still have pulses. Note OUT_A and OUT_B, not MOSFETs Vds. If you do see OUT_A and OUT_B have pulses when Line UVLO < threshold, you need to send your test result and your request to your local TI sales office and request FA process, as there is no way to help to resolve this issue on E2E. 

  • 0 in reply to Hong Huang
    Intellectual 590 points

    Dear

    OK I understand your mentioned that is FA issue.

    Well could you please reply for question about application specified ? 

    How do you think to use voltage detector to insure complete switching during power down process?

    Best regards,  

  • 0 in reply to user5339789
    TI__Guru 74115 points

    Hi,

    Pulling down UVLO or SS should stop the pulses - that is we usually do. Your circuit just doing these and if the pulses cannot be stopped by pulling down UVLO and SS, either the device has something wrong or your secondary-side circuit keeps generating pulses which by pulling down primary-side cannot stop the pulses.

  • 0 in reply to Hong Huang
    Intellectual 590 points

    Dear

    I know what you are saying. Checked by our engineers and it works as you say.

    We also think it's working properly if nothing happens.

    I fully understand your mention of secondary influence.

    Now, for the inconvenient phenomenon that occurs with a very rare probability,

    we tried to add a voltage detection IC (made by TI) as a double check.

    I just want to ask what you think of this method.

    Best regards, Keiichi 

  • 0 in reply to user5339789
    TI__Guru 74115 points

    Hi,

    I am not understanding what you try to do. If you claim when you observed UVLO < threshold and SS pull-down, LM5025 still shows pulses then your circuit cannot work.

    If UVLO < threshold or pulldown SS can stop pulses, then your circuit has no use as your circuit is to make UVLO < threshold or pulldown SS.

    So you need to make clear what caused pulses after UVLO < threshold or pull down SS.    

  • 0 in reply to Hong Huang
    Intellectual 590 points

    Dear

    If pull down the SS or UVLO falls below the threshold, the pulse will stop as you explained. Normally, it works like this, but in rare cases when UVLO is in the error range near the threshold value, it behaves unexpectedly like a restart, so voltage detection is added.

    Regards, Keiichi Takahashi

  • 0 in reply to user5339789
    TI__Guru 74115 points

    Hi,

    It sounds like the issue is your design UVLO does not have enough historesis. You may try add some more hysteresis to see if ok without your added circuit.

    But if you want stay with your added circuit that is your option too.

    Based on your description the device does not have the issue as the issue is due to the UVLO hysteresis not enough.

  • 0 in reply to Hong Huang
    Intellectual 590 points

    Hi

    Now that I have the plot, I will send it to you here.

    You can see the plot where the pulse is output even after UVLO goes down to Low. But the probability of it happening was less than 0.5%. According to the engineer, I have tried adjusting the hysteresis several times. But he says he couldn't solve it.

    Well We don't think it's just a problem with the LM5025, we think there could be secondary circuit implications and other concerns as you explained. So again, I was convinced that if I dropped SS to L with voltage detection and latch circuit, such a restart problem would not occur, so I would like you to agree.

    regards, Keiichi 

    201228.docx

  • 0 in reply to user5339789
    TI__Guru 74115 points

    Hi,

    I only support our device associated . If the secondary side circuit has problems as you use a different vendor device you need to talk to that vendor.

    If you see pulses after pull down SS and UVLO< threshold, you need to go FA.

    We cannot comment other vendors device or your external circuit can solve other vendor circuit issue or not.  You can test to find or ask other vendors.

  • 0 in reply to Hong Huang
    Intellectual 590 points

    No No, I would like to combine with TI's voltage detector ICTPS3710DDC and LM5025.

    I would like to ask you to comment that there is no problem with that combination.

    Regarding shipping to FA, it rarely occurs, so I think that it will be a good product in the judgment.

    I've visited major device vendors since I found the problem, but I couldn't find a comprehensive solutions.

    Therefore, I finally decided to use an external component (ie TPS37100).

    Please comment. If so I will close this thread.

    regards, 

  • 0 in reply to user5339789
    TI__Guru 74115 points

    Hi,

    If pulling down SS or making UVLO < threshold then the pulses stop, then your circuit is ok.

    If pulling down SS or making UVLO < threshold, you still see pulses, no matter always or sometimes, your circuit cannot work.

    You need to test to confirm if your circuit works or not. I cannot get your consistent description so you need to test to confirm by yourself.

    Again, if pulling down SS, or making UVLO < threshold, you stil see pulses, your circuit cannot stop the pulses, then your circuit cannot work . You need to test to find out.