• State Resolved
  • Locked Locked
  • Replies 24 replies
  • Answers 8 answers
  • Subscribers 62 subscribers
  • Views 751 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

LM5025C: Idea to use precision voltage detector and latch to control surge and timing

LM5025C: Unexpected behavior

user5339789
Intellectual 590 points
Part Number: LM5025C
Other Parts Discussed in Thread: LM5025,

The content I posted last time was an idea to solve the unexpected behavior.Today I will provide you with more detailed information.

The phenomenon is that even though the voltage is below the UVLO set voltage, it restarts and the voltage becomes much higher than the switching voltage, resulting in damage to the gate driver.

Let me show you waveforms. Fig 1 is shown SW Vds and Vin. You can see both of Vds stopped, then restart during 1-2ms. We worry that restarted Vds is greater than original Vds.

Fig 2 is extended time domain. Fig 3 is secondary side waveform. Again Voltage range is over 150V... Fig 4 is observation UVLO, Vin and Vds.

We can see these phenomena around 20-30% frequently.

SO we would like to know what there is known behavior, how do you think ? Then if we cannot expect to operate UVLO, we would like to use a voltage detector instead of the controller feature.

regards,201214_WaveForms.docx

  • 0
    TI__Guru 74115 points

    Hi,

    Can you provide your schematics for my review and to understand how the issue is introduced?

  • 0 in reply to Hong Huang
    Intellectual 590 points

    Hi

    Attached is a simplified schematic of our experimental (Actually another peripherals almost disabled.

    Plot drawing is shown at power down, but note is that we can see very high voltage surge when activated.

    regards, 

    ACF-PS_desc-P4.pdf

  • 0 in reply to user5339789
    TI__Guru 74115 points

    Hi,

    Your schematics is too simplified to provide useful info for analysis. Anyway, the primary switch-node high voltage spikes during Line UV off are usually due to the secondary SR regenerating energy stored in Cout back to the primary side. If you use control-driven SR, one way to limit the energy regeneration is to turn off SR drive right after Line UV.

    Any further analysis needs a relative full schematics.  

  • 0 in reply to Hong Huang
    Intellectual 590 points

    Hello

    Yes we expected that primary controller goes off when power down then secondary controller and FETs go to off.

    However your controller seems to be different behavior ( operate for a while even through power down). 

    That is why I am sending a message to you. Therefore we are trying to use voltage detector to find Vin goes off.

    Could you please give your comment?

    regards, 

    8883.ACF-PS_00-c_sch.pdf

    ACF-PS_desc-P4-1.pdf

  • 0 in reply to user5339789
    TI__Guru 74115 points

    Hi,

    After Line UV, the controller still running for a while (should be following voltage drop on SS pin, called soft stop). The feature is to work with self-driven SR. If you use control driven SR, you should generate a signal to turn off your control driven SR MOSFETs.

    In self-driven SR, there is no way to turn off SR MOSFETS so keep primary side running for a while after Line UV, it can help to make the regeneration in control manner.

    So if you add a circuit to turn off your control driven SR MOSFETs, the circuit should help to eliminate the high voltage spikes, or reduce the magnitudes.

  • 0 in reply to Hong Huang
    Intellectual 590 points

    Dear Hong Huang,

    Thank you for your quick reply.

    You agreed to add circuit to stop SR MOSFET immediately. Do you have any recommended chip and circuits ?

    Application schematics made by TI will be more helpful to start redesigning. 

    Our engineer is considering on the primary side to use voltage detector and latch into UVLO pin then we expect to control stop timing to eliminate large output surge voltage. 

    I am looking forward your comments.

    regards, Keiichi 

  • 0 in reply to user5339789
    TI__Guru 74115 points

    Hi,

    I think you need to add a voltage comparator to detect LineUV, then after detect LineUV, you can pull down SS or RAMP using a small MOSFET or a bipolar transistor to stop PWM right away. You can use the LM5025 VCC to bias your detector and pull down circuit, but when VIN drops < 13V, the VCC bias may be lost. So you need to make sure your secondary SR keeps no switching. But as now VIN < 13V, so even if there is some regeneration, the primary switch-node voltage may not rise up too much. You may add a small dummy load on your secondary to help dissipate some energy in Cout. You can also add a small zener to clamp switch-node.

    I think each design needs some special considerations for that particular design so I can only provide the idea how to deal with this issue since each design still needs to test the resulted circuit with balance of cost and MOSFET voltage ratings. 

  • 0 in reply to Hong Huang
    TI__Guru 74115 points

    Sorry, you should only pull down SS, not RAMP, to stop PWM right away.

  • 0 in reply to Hong Huang
    Intellectual 590 points

    Dear Hong Huang,

    Thank you for your prompt reply. I got it your mentioned.

    Still we have several questions its behavior. 

    You mentioned this controller has "soft stop" as a feature, we would like to know more details, could you please explain?

    1) You expressed " for a while" controller running after power down, did you describe this feature on the data sheet?

    2) Do you find how long does it take during "soft stop"? It is OK ideal or design basis. 

    3) We do not understand why phenomena is NOT every time. (We observed occurred 1/3 to 1/4) 

    4) We can see UVLO threshold ( or Hysteresis) is not so stable, what is unstable factor.

    As you may know we will not add component if possible, and if still consider to operate UVLO, we might implement very simple circuits. I mean case by case basis we may use UVLO alternatively. 

    Best regards, Keiichi    

  • 0 in reply to user5339789
    TI__Guru 74115 points

    Hi,

    I also do not think this device shows the feature of soft stop. I just describe what you see.  The soft stop should be based on the capacitor voltage discharge on SS pin. You may measure SS pin voltage during LineUV to check if the switching is controlled by SS and the devic bias UVLO off.

    It looks to me you would need SS pull down to turn off PWM and SR.

  • 0 in reply to Hong Huang
    TI__Guru 74115 points

    As you mentioned not every unit has the delay of PWM off, can you measure UVLO during LineUV? The UVLO threshold has a tolerance so some devices delay may be due to the lower UVLO threshold.

    Your original idea to pull down UVLO with an accurate Vin detection should still be needed unless you can tolerate the UVLO threshold tolerance.

  • 0 in reply to Hong Huang
    Intellectual 590 points

    Hello

    Thanks for your reply

    We still have a question. I think I asked you before, but I don't think you have answered about the behavior of the UVLO function. You have seen the waveform before, and the power is down and UVLO works, and the voltage disappears once, but why does the high voltage spike still occur after 1-2 ms.

    According to the engineer, the LM5025 is still output signal after the power down, and spikes are occurring again during that time. You should think that this controller is strange, but what do you think?

    regards, Keiichi

    8787.201214_WaveForms.docx

  • 0 in reply to user5339789
    TI__Guru 74115 points

    Hi,

    Can you show LM5025C UVLO-pin signal waveform in the same file? Please make sure to show UVLO-pin voltage so you can tell if UVLO-pin voltage value is below or above its on and off threshold.

  • 0 in reply to Hong Huang
    TI__Guru 74115 points

    I assume it is resolved. Otherwise, please start a new thread.

  • 0 in reply to Hong Huang
    Intellectual 590 points

    No I do not think so.

    Still have a question about UVLO, last time you requested to get waveform of it but unfortunately our engineer have not gotten recently relation of Vout and UVLO.

    Now I believe he is trying to get this plot.

    Well We want to know why very high voltage spike occur in spite of to be off when after power down.

    Sometime you explained that circuit might discharge when power down, due to charged output capacitor.
    However we can see some times this phenomena even if using simplified circuit. Clearly we are thinking secondary circuit is not related.

    I will separate thread if your side is better.
    BTW when are you going to have Xmas holidays ?

    regards, Keiichi

     

  • 0 in reply to user5339789
    TI__Guru 74115 points

    Hi,

    Ok, when you have your circuit and waveform ready, you can continue the discussion. For now, I close this thread.

  • 0 in reply to Hong Huang
    Intellectual 590 points

    Hello

    May I continue to use this thread ?  Attached is plot waveforms SW, UVLO, and Vin when power down.

    This behavior is shown in upper plot. Looks like UVLO already goes down and may not be restart. But occurred High voltage spike on Main-SW.

    201222.pdf

    Please send back me your comment.

    regards, Keiichi 

  • 0 in reply to user5339789
    TI__Guru 74115 points

    Can you judge if LineUV voltage when switching back? I cannot judge. Basically you need to judge if LineUV is back to ON or not.

  • 0 in reply to Hong Huang
    Intellectual 590 points

    UVLO voltage is not changed even if occurred high voltage spike on the SW node, according to our engineer.

    Is this light operation of UVLO?

  • 0 in reply to user5339789
    TI__Guru 74115 points

    If UVLO does not change, can you tell if UVLO is below off threshold (<2.44V) when switching comes back?

  • 0 in reply to Hong Huang
    Intellectual 590 points

    Yes UVLO is keeping below threshold but switching restart again... You can see also Vin goes down continuously.

    regards, Keiichi 

  • 0 in reply to user5339789
    TI__Guru 74115 points

    If UVLO below its threshold, you can check OUTA to see if it has pulses. As UVLO < threshold, OUTA should not have pulses.

    If you confirm OUTA (or OUTB) does not have pulses, then the issue is not from LM5025C.

    The issue is due to the secondary-side. So you need to check if your secondary-side SR MOSFETs somehow turn-on and -off. If you do see the SR MOSFETs on/off, you need to check why your secondary side driver keeps on/off.  

  • 0 in reply to Hong Huang
    Intellectual 590 points

    As far as we know, we can see there are output pulse at OUTA/B even if UVLO be down to continuously.

    Le me double check but therefore, operation is not right, LM5025 has issue ........

    regards, Keiichi Takahashi

  • 0 in reply to user5339789
    TI__Guru 74115 points

    If you are sure OUTA and OUTB pulses are still there with UVLO < off threshold, what you can do is to change LM5025C to a new device. If you still see this issue, you need to contact your local TI sales office, to ask their support for failure analysis. When UVLO < off threshold, OUTA and OUTB should not have pulses. If you do see, then the devices you have are with problems. So you need to contact your TI local office to move further. E2E cannot solve this issue.

    So I will close this thread and you need to move on to your TI local sales office for further support.