LM25145: LM25145 Behavior Issue, Need Debugging Help

Hi Nick,

Hard to see the values in the schematic. Please complete and send the LM25145 quickstart calculator file (it's available by download from the product folder). This will help us understand Vin range, Fsw, compensation, power losses, etc.

The FB voltage should regulate at 0.8V. Also, I recommend increasing Cout to at least 2 x 100uF.

Regards,

Tim

Thanks Tim for the reply,

I filled in the datasheet as requested:

LM25145 Wide Vin Synchronous Buck Controller Quickstart Calculator r12-7.zip

Hi Nick,

I'm unable to open that file. Please resend and save as a xlsm file.

Ti mitigate noise, keep the input caps close to the FETs (see app note snva803). Also the VCC and BOOT caps should be close to their respective pins.You can use the EVM layout for prototyping if needed.

Regards,

Tim

Hey Tim,

My design closely follows the EVM model as I used it for my layout reference. If you view the layout pictures, you can see the similarity in the pictures.

There is a pop-up that does not allow me to upload xlsm files as it's not in the list of allowable files to upload. I'm not sure if this is a new feature but zip is the only file I can upload. You can easily unzip the file by right-clicking on it and unzipping it. 

My apologies Tim,

I was confused there for a minute, didn't realize the format had changed. I attached a picture of my GND plane. I do not have my PGND connected directly, should there be a direct connection? 

LM25145 Wide Vin Synchronous Buck Controller Quickstart Calculator r12-7 -XLS.zip

Thank you,

Nick

Hi Nick,

See section 11.1.5 in the datasheet that details ground plane design where the PGND pin is tied to the DAP. Also, there should be vias at the DAP for heatsinking. Currently, there's a single via at pin 12 - does this tie into an inner GND plane? 

Also, ensure that the VCC and BOOT caps are connected closely to the [VCC, PGND] and [BST, SW] pins, respectively.

Regards,

Tim

Hey Tim,

The via next to pin 12 is connected to all 4 GND layers, the via to the left is also connected to all 4 GND layers. Right on the other side is the low side MOSFET. 

In the above picture, you can also see that CVCC is right next to PGND. 

In this picture, I have my RBST and my CBST connected. I have the SW connected via the polypour. 

Is the DAP tied to the internal GND planes too? Maybe the vias are not visible at the DAP. We need to ensure that AGND and PGND are connected.

Regards,

Tim

Yes, the DAP is part of the top polypour which connects pins 5, 9, 12, 15, and 16. The two vias in the picture are the closest to the DAP, but there are more vias nearby. All of my GND vias connect to all 4 GND layers. 

Hi Nick,

The low-side FET is 35nC at Vgs = 7.5V, so the gate drive current is Qg*Fsw = 35nC*1MHz = 35mA. The high-side FEt is 7-8nC, so add another 8mA for that. This seems quite high and exceeds the min VCC current limit spec of 40mA.

Try reducing the switching frequency to 500kHz and use a higher inductance (025uH is low even for 1MHz).

--

Tim

I will try 500kHz. I have some 0.6uH inductors on hand that I can swap, will that be sufficient? 

Use the quickstart calculator and target 30-35% ripple current.

I've ordered a few more inductors in the 1uH range. I'll update you when I receive them and put the board through some more tests. Thank you.