LM25037: CS Pin and Overload Protection Timer not active from 1V - 1.3V of SS voltage

Hi, Victor

Thanks for your interest in TI here. I will be happy to route your request into the appropriate team to support. Please note the team that supports this device is in the US so they will have a delayed response due to the US holiday. Please expect a response in the week of Jan 4^th.

Yunsheng

Hi,

CS pin threshold is 0.25V. Can you explain how 1V threshold is set up in your design?

We need to see your schematics to understand how your circuit behavior.

Sorry typo, it should be SS. I highlighted and corrected it. 

Please provide your schematics for review so to help to understand the behavior.

We changed R18 to 470pF.

Please provide your schematics - I cannot find your schematics.

 I got it.

Please provide your power stage both primary and secondary. Only IC portion does not seem enough info to help the analysis.

Main board

Do you have answer why the CS pin not enabled between 1V to 1.3V of SS pin?

It should so cycle-by-cycle current limit, right? seems to be disabled between that condition.

I have transferred the remote on/off transistor from UVLO pin to SS pin.

Seems to be the same effect.

CS cycle-by-cycle function is disabled between 1-1.3V of SS (soft start) pin.

Where is +15_CTRL in your circuit? I cannot find it.

It is from AUX smps that is powered by PFC 380V.

So 380V PFC -> Aux -> 13V.

Then we do remote ON on UVLO pin by opening the transistor collector.

The 380V PFC is also the input to the DC-DC main board.

Pls check main board https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/196/Main_5F00_SCH.png 

J8 pin1 is the 13Vcc control supply voltage.

Where is Q3 Source pin connected (it looks Q3 does not connect any return path of power stage loop?

Also, your circuit only shows Q5 to current sense transformer. Why you do not sense Q3 current?

Q3 is connected by a wire from J6 to J5 in opposite flux direction of SEN1.

So the output of SEN1 is full bridge and rectified by D12-13.

Do not worry about the main power stage, we have few modules of the same topology and design that's been running for >10yrs already.

What I do not understand is why the CS pin is not triggered when SS pin is between 1V - 1.3V when the output is shorted and we start the controller by UVLO pin.

This test had been carried out by our reliability team while we do cost reduction by reducing the rating of the output rectifier.

Then problem we found out about the SS pin 1V-1.3V seems to disable the CS pin and Overload Protection Timer.

What is your CS pin voltage waveform and RES waveform when SS pin is between 1V and 1.3V?

If J6 to J5 is connected, then Q3 current is not sensed when Q3 and Q8 conduct, right? So you only sense half cycle current?

I think you need to zoom in your test waveform to check your CS pin voltage waveform along with RES waveform to see if CS pin over current limit exists during RES rise up, or sometimes, CS pin actually not reaches over current limit, that is, if CS over current persists or not when you use UVLO to start your converter with output short.

Your green waveform (RES) does not keep rising when you use UVLO to start your converter with output short. RES in your test only rises up to 2V very quickly at close to 10ms. This is different from your steady state operation when short happening where RES rises up quickly.

In other words, your waveforms show RES stays much lower when < 10ms, and only suddenly rises up at very close to 10ms. As RES rise needs CS over limit persists, you need to check if CS pin over limit persists - your waveform of RES seems your CS over limit does not persist. If so, the issue is not due to the SS but due to your CS sense. So you need to test  and find out.   

I think you need to zoom in your test waveform to check your CS pin voltage waveform along with RES waveform to see if CS pin over current limit exists during RES rise up, or sometimes, CS pin actually not reaches over current limit, that is, if CS over current persists or not when you use UVLO to start your converter with output short.

Your green waveform (RES) does not keep rising when you use UVLO to start your converter with output short. RES in your test only rises up to 2V very quickly at close to 10ms. This is different from your steady state operation when short happening where RES rises up quickly.

In other words, your waveforms show RES stays much lower when < 10ms, and only suddenly rises up at very close to 10ms. As RES rise needs CS over limit persists, you need to check if CS pin over limit persists - your waveform of RES seems your CS over limit does not persist. If so, the issue is not due to the SS but due to your CS sense. So you need to test  and find out. 

A few clarifications (based on your the last waveforms):

I think you need to zoom in your test waveform to check your CS pin voltage waveform along with RES waveform to see if CS pin over current limit exists during RES rise up, or sometimes, CS pin actually not reaches over current limit, that is, if CS over current persists or not when you use UVLO to start your converter with output short.

Your green waveform (RES) does not keep rising when you use UVLO to start your converter with output short. RES in your test only rises up to 2V very quickly at close to 10 31ms (from very left edge of your waveform screen). This is different from your steady state operation when short happening where RES rises up quickly.

In other words, your waveforms show RES stays much lower when < 31 10ms, and only suddenly rises up at very close to 10ms. As RES rise needs CS over limit persists, you need to check if CS pin over limit persists - your waveform of RES seems your CS over limit does not persist. If so, the issue is not due to the SS but due to your CS sense. So you need to test  and find out if CS does not persists to over limit and cause RES not rise up over 2V which is required to stop PWM. 

J6 is connected to J5 by a wire inserted inside the core of SEN1 in opposite direction. It is a manual assembly.

The wire and current that is in opposite direction is also opposite in flux, thus, I have a bridge rectifier and the rectified signal goes to CS pin.

We know that secondary current is almost the same as the primary current by mutual induction of the transformer T1.

And primary current is same as the secondary current by the same principle of mutual induction of current sense transformer SEN1.

So I have deduced that the cycle-by-cycle in CS pin was triggered to around 17A (secondary current) plus some variance.

This variance can be tuned by the current sense resistors and R28 & R29 in the control circuit.

By the way, R28 & R29 further divide the voltage from the current transformer SEN1 to CS pin of the IC which I can tune to my liking.

After I have tuned those, I know exactly when the load current will trigger the CS pin.

This can be seen here >>> https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/196/IMG_5F00_20201217_5F00_150618.jpg

RES pin will charge for around 8 triggered pulses on CS pin. Pls check, 8 pulses then RES pin will get activated.

Also, we can observe that there are some duty cycle limit due to CS pin more than 250mV.

But this is not happening when start-up output short as seen here >>> https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/196/IMG_5F00_20201218_5F00_112623.jpg

It is exceeding the 17A trigger level I have set. There may be some blanking situation between 1.V-1.3V of SS pin.

Later, if I find a time, I will probe the CS pin, which I absolutely believe, that it is exceeding 250mV.

Your test result show RES does not reach 2V until at about 31ms. Based on the datasheet, RES capacitor is being charged up along with CS pin current limit persists, see datasheet, page 12, figure 13.

I think you need to check and measure your CS pin voltage to confirm the CS pin current limit status persists. Again, your test result shows RES does not consistently being charged up, and only at very close to 31ms RES suddenly rise up very quickly to 2V then PWM stops. 

You are correct, that is the BIG question.

1. Why only after 10mS the RES pin starts to charge? From green line to the end.

another BIG question:

2. Why the pulse-by-pulse is not active? From green line to the end.

Pulse-by-pulse should limit the current by 17A, but it does not. Yellow line limit.

When it reach 17A timer RES pin should start to charge, but only after 10mS, where the current is already 40A.