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UCC28180: Improving ICOMP/current harmonics performance with Type-II (C + RC) network?

Part Number: UCC28180


We have a 400Hz application using UCC28180. Overall, it's been easy to use, but we are having some difficulties improving the current distortion and harmonic content at about the 15th harmonic. The standard we are attempting to comply with requires testing with a non-sinusoidal input voltage wave-shape. This is to test whether the equipment can still maintain good current-distortion even when the voltage is heavily distorted. With a 0% THD sine wave, the current harmonics are great, very low ITHD. But, with about ~8% VTHD, the ITHD at ~15th harmonic (6KHz) is not so great. We are wondering if maybe the current loop is oscillating causing a 6KHz component on the input current wave. Is it reasonable? Possible?

Of course, with a distorted input voltage, you cannot expect that the input current will not be distorted. So, the standard basically the current harmonics limits are "added" to the actual voltage distortion in each harmonic. This is already accounted for.

The bulk of the issue was actually improved by reducing the total input capacitance in the input filter...which causes distortion due to abrupt change in voltage (dv/dt) with distorted (clipped) input voltage.

But, we still need to improve the distortion.

We noted in SLUUAT3B (UCC28180EVM), an R and C are left unpopulated across ICOMP. In a typical compensation network, this converts a 'C only' Type-I network into Type-II. This adds phase boost and increases mid-band gain. Can anyone advise what frequency the zero should be set to? The BOM shows 100R + 0.1uF, which sets fz1 = 15.9KHz. If we have issues around 6KHz, should this be set lower? For instsance, 150R + 0.22uF = 4.8KHz.

What does this network hypothetically help with? Any ideas how how to approach?



  • Some additional information.

    We are trying to meet DO-160. The equipment has a ~120W peak power demand, but normal operating condition is around 60W, so we need to meet the harmonics requirements at 60W with an inductor sized for at least 120W.

    Below you can see the distorted voltage waveform (magenta) and resulting current waveform (blue). We know some of the "wiggles" on the current waveform are from the input filter (on the AC side of the bridge). The filter has already been reduced to the lowest possible total capacitance.


  • Hi, Tim

    If the input frequency is 400Hz, the compensator on ICOMP and VCOMP should be optimized. I've assigned your post to dedicated AE, please expect a reply by day of Wednesday.



  • Hi Yunsheng,

    Thank you for your reply. Basically we are trying to understand reasonable starting values for ICOMP/VCOMP for 100W/400Hz. We are interested to know what values are needed for Type-II ICOMP compensator.



  • And here is our current schematic with values. Thanks.

  • Good news...Sorry for so many posts and scattered thoughts. We were able to reduce the distortion by reducing ICOMP resistor to 1000pF. This sets the crossover frequency at about 12KHz. Our switching frequency is 100KHz. We are going to check if it can be improved by further reduction. I think we shouldn't move the crossover frequency above 20%*fsw...generally.

    Which load conditions and input voltage/frequencies represent the worst case condition for current control loop stability? I imagine 400Hz is worst, but not sure about load and input voltage.

    We are still curious about Type-II compensator on ICOMP and any other ideas to improve the distortion, to give us more ITHD margin.


  • Hi Tim,

    for a 400Hz input PFC, you need much less input filter cap on input filter circuit and need a much higher PFC voltage loop.

    So my suggestion for Vcomp can be we set the bandwith width at around 80Hz, and the zero on Vcomp set at below 80Hz, you can start with 50Hz. The high frequency pole can be set at 20kHz.

    For Icomp, If you also choose type-ii, and want to increase the stability at 6Khz,  I would suggest start with Zero at 3kHz to higher the phase margin at 6kHz.

    hope this helps you.

  • Hi David,

    Thanks for your reply. On second thought, I actually don't think there's a current loop instability at 6KHz...I think the waveform just makes some harmonic content at 15th harmonic. If truly unstable, I think oscillation would be stronger, but just a guess.

    IEEE has a paper " On the Zero-Crossing Distortion in Single-Phase PFC Converters by Jian Sun, 2004". Jian describes some issues with 400Hz and current control loop. In his example, he set the loop cross-over frequency to ~10KHz, and the bad waveform is improved. When he sets it to about 4KHz, the waveform looks worse. That's why we decreased ICOMP to 1000pF. Distortion in 15th harmonic dropped from 1.5% to 1.0%.

    I guess we are confused...what is the relevance of the VCOMP to input current wave-shape?

    We will try your suggestions. We already increased the gain and bandwidth compared to application note circuit, which is quite slow. We will try 1uF -> 0.68uF, 100K -> 240K, and 68nF -> 10nF

    Can you provide some starting values for ICOMP with Type-II? Or, what are the equations needed?


  • Hi Tim,

    slower voltage loop helps on ithd but influence a lot during load transient in a real case. That is why I recommend to increase the bandwidth of voltage loop.

    For Icomp with Type-II, the cap between Icomp pin can be start from 1.5nF, then to 1nF.

    the RC can be start with 100ohm+470nF with 3.3K zero and slightly decrease the 470nF.

    For the 100W boost PFC, if you use UCC28180 calculator in the TI website and select the inductor current ripple factor with 0.225, then the PFC inductor is at 3.14mH. But from your schematic, only 1.2mH is used, I suggest you increase PFC inductor value to allow less PFC current ripple this helps a lot for ITHD.