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TLC5945 TLC5943 CASCADING up to 256 chips

Other Parts Discussed in Thread: TLC5945, TLC5943, TLC5951

Hello,
My customer wouldlike cascading  up to 160 Chips ,60Hz refresh .
Datasheet of TLC5945  (SLVS755) , page18 , give  F(SCLK) mini = 193 x 160 x 60 =   18  852 800 hz
That is far under the Max clock of 30Mhz of TLC5945 .
 
1> How to explain the sentense page18 : ?
<The maximum number of cascading TLC5945 devices depends on the application system and is in the range of 40 devices>

2> Could you confirm this calculation is also usable for the TLC5943 , as this calculation is not Included in the doc ?
(this is to have possibility to use the 16Bits PWM)

 

 

Thanks for Help,
Michel VINEZ DFAE

  • Hello Michel,

    The problem with cascading the parts is that the data is shifted through all parts and the SCLK signal is directly connected to all parts at the same time. This generates some issues if you cascade a lot of these parts in series. Especially the SCLK signal might get rounded edges and slower slopes due to the board parasitics.

    You must be careful to ensure the TLC594x setup and hold requirements are met.  If your signal drive strength is too low, the signal edges will be rounded due to the board capacitance on the data and clock lines.  There is no requirement to buffer the clock or any other signals.  However, depending on your specific drive strengths, board capacitances, clock speeds, timing between signals, you may need to buffer your signals to meet the TLC594x timing requirements.  If you are at the limits of the setup and hold requirements and have rounded edges on your clock and data signals, you might be able to shift the timing between your signals to resolve the problem.  It may require a buffer.

    So the sentence on page 18 gives the experience on the above problem. If you are cascading such a lot TLC594x devices, I would recommend to add clock buffers to make sure that the timings are fulfilled. The number might be a little different on TLC5943 compared to TLC5945 because of different delays in the system, but you will face a similar issue.

    Best regards,
    Brigitte

  • THANKS , Brigitte !
    This is EXACTLY the info we are looking for !
    So we need to put some  CLOCK FAN OUT Buffer in the design.
    I Cannot find easily a Chip on Texas web , with  a mini Frequency of 5Mhz ( the Mini clock frequency the customer want to use)
    And the possibility to adjust individually the Phase of each OutPut
    Do you have any idea ?
    Michel

  • Hello Michel,

    Sorry, but I am not the right person to recommend clock devices. I would recommend you to ask the question in the clock forum, there you will get a better answer.

    Best regards,
    Brigitte

  • Hello,
    I am designing a board that has a significant cost and would not wait to try it to know if I need a buffer or not. I would like information about the input impedance of the clock lines to make sure I do not charge my clock source. And it is not possible to establish the characteristics of buffer.

    I have to connect 32 tlc5951 series, I'll need a buffer?

    Best regards,

    Ezequiel Picca

  • Hello Picca-san,

    It's no problem for driveability of TLC5951 between IC to IC if SCK can keep a timing on data sheet.

    But SCK timing is depend on controller driveability , PCB layout or line capacitor on PCB board whether it need buffer or not for connect 32pcs.

    We are suppoirting IBIS model as simulation tool for released device.

    You can get on TI web site as below.

       http://www.ti.com/product/tlc5951   

    Tools & Software Models (2)

    Best Regards

    K.Narisawa